Abstract: Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.

Abstract: Packages and packaging techniques are described in which a patterned carrier substrate can be used to create a reconstituted fanout substrate with a topography that can accommodate components of different thicknesses. In an embodiment, a wiring layer is formed directly on a multiple level topography of a molding compound layer including embedded components.

Abstract: One or more stud bumps may form a conductive column to a component having back side metallization. In an embodiment, the column of stud bumps may be about 130 um vertically (Z-direction). Providing a microelectronics package with a column of stud bumps electrically connected to a component having back side metallization may provide a cost effective electrical interconnect and may enable the incorporation of components of different thicknesses, including that the component thicknesses are independent of each other, in a single fanout package, while providing a thin package profile and back side surface finish integration.

Abstract: Wafer level passive array packages and modules are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.

Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

Abstract: Packages and packaging techniques are described in which a patterned carrier substrate can be used to create a reconstituted fanout substrate with a topography that can accommodate components of different thicknesses. In an embodiment, a wiring layer is formed directly on a multiple level topography of a molding compound layer including embedded components.

Abstract: One or more stud bumps may form a conductive column to a component having back side metallization. In an embodiment, the column of stud bumps may be about 130 um vertically (Z-direction). Providing a microelectronics package with a column of stud bumps electrically connected to a component having back side metallization may provide a cost effective electrical interconnect and may enable the incorporation of components of different thicknesses, including that the component thicknesses are independent of each other, in a single fanout package, while providing a thin package profile and back side surface finish integration.

Abstract: Wafer level passive array packages, modules, and methods of fabrication are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.

Abstract: An optical module may be formed on a wafer. The wafer may include a substrate and one or more optical components encapsulated, at least partially, by the substrate. Each of the optical components are configured to emit or sense light. The wafer may also include one or more printed circuit board (PCB) bars encapsulated, at least partially, by the substrate allowing electrical conductivity from a first side of the substrate to a second side of the substrate. The wafer may also include at least one redistribution layer to electrically couple at least one of the optical components to at least one of the PCB bars.

Abstract: A method for manufacturing an optical wafer may include coating multiple optical components with a substrate. The multiple optical components may include a light emitting component and a light detecting component, and each of the optical components may include one or more electrical connections. The method may also include depositing a redistribution layer onto at least one of the electrical connections, wherein the redistribution layer routes the electrical connection within the optical wafer to an external connection. The method may also include depositing a passivation layer over the redistribution layer and depositing a dark photoresist layer on at least the passivation layer. The photoresist layer may operatively reduce optical interference between at least one light emitting component and at least one light detecting component.

Abstract: An optical module may be formed on a wafer. The wafer may include a substrate and one or more optical components encapsulated, at least partially, by the substrate. Each of the optical components are configured to emit or sense light. The wafer may also include one or more printed circuit board (PCB) bars encapsulated, at least partially, by the substrate allowing electrical conductivity from a first side of the substrate to a second side of the substrate. The wafer may also include at least one redistribution layer to electrically couple at least one of the optical components to at least one of the PCB bars.

Abstract: A method for manufacturing an optical wafer may include coating multiple optical components with a substrate. The multiple optical components may include a light emitting component and a light detecting component, and each of the optical components may include one or more electrical connections. The method may also include depositing a redistribution layer onto at least one of the electrical connections, wherein the redistribution layer routes the electrical connection within the optical wafer to an external connection. The method may also include depositing a passivation layer over the redistribution layer and depositing a dark photoresist layer on at least the passivation layer. The photoresist layer may operatively reduce optical interference between at least one light emitting component and at least one light detecting component.