Abstract: A system and method access memory blocks in a memory by receiving a memory transaction request from a processing device. First hash bits of the memory transaction request are compared with second hash bits of a first memory block of a memory. Data associated with the first memory block is output to the processing device based on the comparison of the first hash bits with the second hash bits.

Abstract: A system and method service memory transaction requests by receiving a memory transaction request for a first memory line from a first processor core of processor cores of a processing system. A second processor core of the processor cores is determined to include the first memory line in a shared state. Data of the first memory line is communicated from the second processor core to the first processor core based on determining that the second processor core comprises the first memory line in a shared state.

Abstract: A system and method for mitigating memory transaction conflicts by receiving a first memory transaction from a first processor slice of a processor and a second memory transaction from a second processor slice of the processor. Further, one or more control signals are generated for the first memory transaction and the second memory transaction based on a determination that the first memory transaction and the second memory transaction have a target address associated with a first memory bank of a memory. The first memory transaction is selected to output to the first memory bank based on the one or more control signals.

Abstract: A system and method mitigates conflicts between clean unique requests by receiving a first clean unique request from a first processor core and a second clean unique request from a second processor core. The first clean unique request and the second clean unique request respectively indicate that the first processor core and second processor core request access to a first address of a memory. The memory is coupled to the first processor core and the second processor core. The first clean unique request and the second clean unique request are determined to be associated with the first address. Further, the second clean unique request is converted into a first read unique request based on determining that the first clean unique request and the second clean unique request are associated with the first address. The first read unique requests indicates that the second processor core requests data.

Abstract: A processing system employs a method to order the elements within a memory. Ordering the elements includes receiving an accessed memory element. The accessed memory element is requested by a processor from a memory. Further, the accessed memory element is compared to stored elements within the memory to generate control signals. Gate control signals from the control signals are generated. The order of the stored elements within the memory is updated based on the gate control signals.

Abstract: Merging store instructions for a memory includes receiving a first store instruction having a first address, and determining a first pattern based on a comparison of the first address and a second address of an entry within a buffer. Further, a size field of the entry is updated based on the first pattern. The first address of the first store instruction is merged with the second address within the entry to generate a merged instruction. The merged store instruction is communicated to the memory.

Abstract: A system and method for performing a store to load process includes receiving a first store instruction. The first store instruction includes a first target address, a first mask, and a first data structure. Further, the first target address, the first mask, and the first data structure are stored within a first store buffer location of a store buffer. A first entry identification associated with the first store buffer location is stored within an age buffer. The first data structure is output based on an order of entry identifications within the age buffer.

Abstract: A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.

Abstract: A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.

Abstract: A memory address may be received at an m-way set-associative cache, which may store a set of cache entries. The memory address may be partitioned into a tag, an index, and an offset. The m-way set-associative cache may include a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries. The index may be used to select a first set of entries from the first structure. A first portion of tag bits of the memory address may be matched with the first set of entries. A cache status may be determined based on matching the first portion of tag bits of the memory address with the first set of entries.

Abstract: A computer system and method is disclosed for efficient cache memory organization. One embodiment of the disclosed system include dividing the tag memory into physically separated memory arrays with the entries of each array referencing cache lines in such a way that no two cache lines, which are consecutively aligned in data cache memory, reside in the same array. In another embodiment, the entries of the two memory arrays reference consecutively aligned cache lines in an alternating manner.