Abstract: Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes (“ECC”) and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.

Abstract: Aspects of the invention include techniques for improving the accuracy of access-limited neural network inference in low-voltage regimes. A non-limiting example method includes training a first machine learning model to perform input transformation for reducing low-voltage bit errors for a deep neural network operating in a low-voltage regime. The training includes inputting training data into the first machine learning model such that, in response, the first machine learning model produces transformed training data; inputting the transformed training data into a clean machine learning model and into perturbed machine learning models, the perturbed machine learning models being generated by applying random bit errors to the clean machine learning model; and optimizing the first machine learning model based on a comparison of output of the clean machine learning model and of the perturbed machine learning models compared to groundtruth labels for the training data.

Abstract: A hardware device receives a work request from a guest, the work request identifying a virtual address within a guest address space. The hardware device sends an address translation request to an address translation resource to translate the virtual address to a corresponding physical address in a physical address space. A blocking message is received from the address translation resource based on a determination that the virtual address is a faulty address and the blocking message identifies a source of the faulty address. The hardware device prevents a later address translation request for a later work request from the source based on the blocking message.

Abstract: Embodiments are disclosed of a computer-implemented method. The method includes establishing a computational grid that includes a plurality of computational cells and describes a volume containing a combustible fluid mixture. The method identifies positions in the computational grid of a flame front propagating through the combustible fluid mixture, identifies a set of representative computational cells that can be used as a computational representation of the flame front, and applies a well-mixed-reactor model and a G-equation model to every computational cell within the set of representative computational cells to compute chemical results from combustion of the combustible fluid mixture in the flame front.

Abstract: An example of an apparatus may include memory and an input/output (IO) bus, where an address space of the memory and the IO bus is at least partially organized as a plurality of large pages, and where a large page is organized as two or more sub-pages. In some examples, the apparatus further includes circuitry coupled to the memory and the IO bus to map an IO address to a physical address, and track a modification to a large page at a granularity that corresponds to a size of a subset of the large page. Other embodiments are disclosed and claimed.

Abstract: A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached—where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.

Abstract: Systems and methods for voltage regulation of high voltage direct current systems are provided. In certain embodiments, a system includes a generator that generates alternating current (AC) voltage. The system further includes a power converter that converts the AC voltage into regulated direct current (DC) voltage. Also, the system includes a voltage regulator. In additional embodiments, the voltage regulator includes an AC voltage regulator that regulates the AC voltage generated by the generator. Also, the voltage regulator includes a DC voltage regulator that regulates the DC voltage produced by the power converter. Moreover, the voltage regulator includes a regulator selector that selectively activates one of the AC voltage regulator and the DC voltage regulator based on a current from the power converter and at least one of a voltage of the generator and a voltage of the power converter.

Abstract: A computer-implemented method, a computer system and a computer program product customize generation and application of stress test conditions in a processor core. The method includes receiving a workload at the processor core, where the workload includes a plurality of instructions and the processor core comprises a plurality of macros. The method also includes obtaining macro performance data for each macro in the plurality of macros from the processor core. The method further includes determining a switching activity level for each macro in the plurality of macros when each instruction in the plurality of instructions is run based on the macro performance data. Lastly, the method includes generating a stressmark comprising the plurality of instructions in the workload, where the stressmark is associated with a macro in the plurality of macros when the switching activity level for the macro is above a minimum threshold.

Abstract: Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes (“ECC”) and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.

Abstract: An input transformation function that transforms input data for a second machine learning system is learned using a first machine learning system, the learning being based on minimizing a summation of a task loss and a post-activation density loss. The input data is transformed using the learned input transformation function to alter the post-activation density to reduce an amount of energy consumed for an inferencing task and the inferencing task is carried out on the transformed input data using the second machine learning system.

Abstract: Systems and methods for voltage regulation of high voltage direct current systems are provided. In certain embodiments, a system includes a generator that generates alternating current (AC) voltage. The system further includes a power converter that converts the AC voltage into regulated direct current (DC) voltage. Also, the system includes a voltage regulator. In additional embodiments, the voltage regulator includes an AC voltage regulator that regulates the AC voltage generated by the generator. Also, the voltage regulator includes a DC voltage regulator that regulates the DC voltage produced by the power converter. Moreover, the voltage regulator includes a regulator selector that selectively activates one of the AC voltage regulator and the DC voltage regulator based on a current from the power converter and at least one of a voltage of the generator and a voltage of the power converter.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Abstract: An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.

Abstract: Techniques for address translation cache (ATC) reservation in offload devices are disclosed. In the illustrative embodiment, a processor of a compute device sends a start ATC reservation descriptor to an offload device. The start ATC reservation descriptor includes an identifier associated with a virtual machine for which at least part of an address translation cache of the offload device should be reserved. The offload device establishes a zone in the ATC of the offload device that is reserved for address translations associated with the identifier. Such cache reservation may be used when, e.g., a priority of a task is high or there is a need for critical or important workload to have lower latency and higher throughput.

Abstract: Scalable I/O Virtualization (Scalable IOV) allows efficient and scalable sharing of Input/Output (I/O) devices across a large number of containers or Virtual Machines. Scalable IOV defines the granularity of sharing of a device as an Assignable Device Interface (ADI). In response to a request for a virtual device composition, an ADI is selected based on affinity to the same NUMA node as the running virtual machine, utilization metrics for the Input-Output Memory Management Unit (IOMMU) unit and utilization metrics of a device of a same device class. Selecting the ADI based on locality and utilization metrics reduces latency and increases throughput for a virtual machine running critical or real-time workloads.

Abstract: Systems, methods, and devices for software-driven resource reservation of an input/output memory management unit (IOMMU) are provided. A system may include a peripheral device and a processing device. The peripheral device may be accessible to a virtual machine running on the processing device via direct memory access (DMA) that is translated by an IOMMU). The processing device may run the virtual machine and a virtual machine manager. The processing device also includes the IOMMU, which is configurable to reserve a subset of resources of the IOMMU to the virtual machine based on a descriptor provided by the virtual machine manager.

Abstract: A method (and structure and computer product) to optimize an operation in a Neural Network Accelerator (NNAccel) that includes a hierarchy of neural network layers as computational stages for the NNAccel and a configurable hierarchy of memory modules including one or more on-chip Static Random-Access Memory (SRAM) modules and one or more Dynamic Random-Access Memory (DRAM) modules, where each memory module is controlled by a plurality of operational parameters that are adjustable by a controller of the NNAcc. The method includes detecting bit error rates of memory modules currently being used by the NNAccel and determining, by the controller, whether the detected bit error rates are sufficient for a predetermined threshold value for an accuracy of a processing of the NNAccel. One or more operational parameters of one or more memory modules are dynamically changed by the controller to move to a higher accuracy state when the accuracy is below the predetermined threshold value.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

Abstract: A coarse error correction system for detecting, predicting, and correcting errors in neural networks is provided. The coarse error correction system receives a first set of statistics that are computed from values collected from a neural network during a training phase of the neural network. The coarse error correction system computes a second set of statistics based on values collected from the neural network during a run-time phase of the neural network. The coarse error correction system detects an error in the neural network during the run-time phase of the neural network by comparing the first set of statistics with the second set of statistics. The coarse error correction system increases a voltage setting to the neural network based on the detected error.