Patents by Inventor Karthikeyan Kandaswamy

Karthikeyan Kandaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218655
    Abstract: A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: February 4, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ahmed Essam Hashim, Karthikeyan Kandaswamy, Abhishek Badarinath
  • Publication number: 20230246640
    Abstract: A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.
    Type: Application
    Filed: March 24, 2023
    Publication date: August 3, 2023
    Inventors: Ahmed Essam Hashim, Karthikeyan Kandaswamy, Abhishek Badarinath
  • Patent number: 11641198
    Abstract: A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: May 2, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ahmed Essam Hashim, Karthikeyan Kandaswamy, Abhishek Badarinath