Patents by Inventor Karthikeyan NATARAJAN
Karthikeyan NATARAJAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11574097Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.Type: GrantFiled: April 15, 2021Date of Patent: February 7, 2023Assignee: NVIDIA CORP.Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
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Patent number: 11228490Abstract: An initial set of one or more data stores is selected for storing configuration data of a first client of a configuration discovery service. Configuration data for various items of the client's computing environment are stored at the initial set for a first time period. A configuration item, whose records were being stored at a first data store, is identified as a candidate for a data store change. Storing of at least some configuration data of the item at a different data store is initiated.Type: GrantFiled: December 20, 2016Date of Patent: January 18, 2022Assignee: Amazon Technologies, Inc.Inventors: Theodore Carroll, Karthikeyan Natarajan, Hariharan Subramanian
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Publication number: 20210295169Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.Type: ApplicationFiled: April 15, 2021Publication date: September 23, 2021Applicant: NVIDIA Corp.Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
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Patent number: 11010516Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.Type: GrantFiled: August 9, 2019Date of Patent: May 18, 2021Assignee: NVIDIA Corp.Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
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Patent number: 10901657Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.Type: GrantFiled: November 29, 2018Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Saravanan Sethuraman, Sumantra Sarkar, Karthikeyan Natarajan, Tathagato Bose, Adam J. McPadden
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Publication number: 20200174696Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: SARAVANAN SETHURAMAN, Sumantra Sarkar, Karthikeyan Natarajan, Tathagato Bose, Adam J. McPadden
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Patent number: 10659520Abstract: Various systems and processes may be used for virtual disk importation. In particular implementations, systems and processes for virtual disk importation may include the ability to receive a request from a customer of a service provider network to import a virtual disk, which is accessible over a communication network, into the service provider network. The systems and processes may also include the ability to download a portion of a virtual disk file corresponding to the virtual disk, determine the type of the virtual disk by analyzing the downloaded portion, and determine the size of the virtual disk by analyzing the downloaded portion. The systems and processes may further include the ability to determine whether the virtual disk is supported by the service provider network based on the determined type of the virtual disk and download the virtual disk if the virtual disk is supported by the service provider network.Type: GrantFiled: June 30, 2015Date of Patent: May 19, 2020Assignee: Amazon Technologies, Inc.Inventors: Ekanth Sethuramalingam, Venkata Satya Siva Kumar Balaga, Karthikeyan Natarajan
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Patent number: 10657306Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.Type: GrantFiled: July 24, 2019Date of Patent: May 19, 2020Assignee: NVIDIA Corp.Inventors: Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan
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Publication number: 20200151289Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.Type: ApplicationFiled: August 9, 2019Publication date: May 14, 2020Applicant: NVIDIA Corp.Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
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Publication number: 20200151288Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.Type: ApplicationFiled: July 24, 2019Publication date: May 14, 2020Applicant: NVIDIA Corp.Inventors: Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan
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Patent number: 10473720Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.Type: GrantFiled: October 27, 2016Date of Patent: November 12, 2019Assignee: Nvidia CorporationInventors: Pavan Kumar Datla Jagannadha, Dheepakkumaran Jayaraman, Anubhav Sinha, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Mahmut Yilmaz
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Patent number: 10444280Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.Type: GrantFiled: October 27, 2016Date of Patent: October 15, 2019Assignee: NVIDIA CORPORATIONInventors: Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Sailendra Chadalavda, Jonathon E. Colburn, Kevin Wilder, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha
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Patent number: 10362039Abstract: A computing resource service provider may receive, from a user client connected to an on-premises network, a security document specifying one or more user roles defining a level of access to customer resources within the on-premises network. In response, the service provider may generate and provide the user client with a cookie specifying the user roles and including an address for an interface within the service provider network. The service provider may receive a request from the user client to access one or more customer resources hosted by the service provider. The request may include the cookie previously provided to the user client. Accordingly, the service provider may extract the user roles from the cookie and determine, based at least in part on these user roles, whether to fulfill the user client request.Type: GrantFiled: December 19, 2016Date of Patent: July 23, 2019Assignee: Amazon Technologies, Inc.Inventors: Wesley Marlin Sutton, Apolak Borthakur, Derek Avery Lyon, Raviprasad Venkatesha Murthy Mummidi, Karthikeyan Natarajan
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Patent number: 10212031Abstract: At a configuration discovery service, a unique service-side identifier is generated for a configuration item based on analysis of a data set obtained from a first data source. A determination is made that a second data set, which does not contain the service-side identifier and is obtained from a different data source, also includes information pertaining to the same configuration item. A coalesced configuration record for the configuration item is prepared. The coalesced configuration record is stored at a repository and used to respond to a programmatic query.Type: GrantFiled: June 22, 2016Date of Patent: February 19, 2019Assignee: Amazon Technologies, Inc.Inventors: Hariharan Subramanian, Vijay Dheeraj Reddy Mandadi, Cristian Gabriel Gafton, Karthikeyan Natarajan, Ramapulla Reddy Chennuru, Kashfat Khan, Venkata Satya Siva Kumar Balaga
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Patent number: 9979596Abstract: Configuration items of an environment for a client of a configuration discovery service are identified. A view category is selected for the target environment. A set of configuration items for which information regarding recent configuration changes is to be provided is identified. Data which can be used to display a graphical representation of at least a portion of the environment and the configuration changes is transmitted.Type: GrantFiled: June 22, 2016Date of Patent: May 22, 2018Assignee: Amazon Technologies, Inc.Inventors: Hariharan Subramanian, Vijay Dheeraj Reddy Mandadi, Ramapulla Reddy Chennuru, Karthikeyan Natarajan, Gunja Agrawal, Long Kim Do
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Publication number: 20170373933Abstract: At a configuration discovery service, a unique service-side identifier is generated for a configuration item based on analysis of a data set obtained from a first data source. A determination is made that a second data set, which does not contain the service-side identifier and is obtained from a different data source, also includes information pertaining to the same configuration item. A coalesced configuration record for the configuration item is prepared. The coalesced configuration record is stored at a repository and used to respond to a programmatic query.Type: ApplicationFiled: June 22, 2016Publication date: December 28, 2017Applicant: Amazon Technologies, Inc.Inventors: HARIHARAN SUBRAMANIAN, Vijay Dheeraj Reddy Mandadi, CRISTIAN GABRIEL GAFTON, Karthikeyan Natarajan, Ramapulla Reddy Chennuru, Kashfat Khan, Venkata Satya Siva Kumar Balaga
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Publication number: 20170373932Abstract: Configuration items of an environment for a client of a configuration discovery service are identified. A view category is selected for the target environment. A set of configuration items for which information regarding recent configuration changes is to be provided is identified. Data which can be used to display a graphical representation of at least a portion of the environment and the configuration changes is transmitted.Type: ApplicationFiled: June 22, 2016Publication date: December 28, 2017Applicant: Amazon Technologies, Inc.Inventors: HARIHARAN SUBRAMANIAN, Vijay Dheeraj Reddy Mandadi, Ramapulla Reddy Chennuru, Karthikeyan Natarajan, Gunja Agrawal, Long Kim Do
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Patent number: 9778952Abstract: A customer network client detects, through a user interface, selection of a graphical representation of a set of virtual machine images and an indication to migrate this set of virtual machine images to an off-premises network managed by a computing resource service provider. In response, the client generates a set of application programming interface calls, which may be transmitted to the service provider and causes the service provider to convert the selected images for use within the off-premises network. The client monitors fulfillment of the calls and, upon determining that the calls has been fulfilled, updates a portion of the user interface associated with the computing resource service provider to indicate that the images may be instantiated within the off-premises network.Type: GrantFiled: June 27, 2014Date of Patent: October 3, 2017Assignee: Amazon Technologies, Inc.Inventors: Wesley Marlin Sutton, Raviprasad Venkatesha Murthy Mummidi, Karthikeyan Natarajan, Long Kim Do, Derek Avery Lyon, Keshav Sethi Attrey, Hariharan Subramanian
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Publication number: 20170115351Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.Type: ApplicationFiled: October 27, 2016Publication date: April 27, 2017Inventors: Pavan Kumar Datla Jagannadha, Dheepakkumaran Jayaraman, Anubhav Sinha, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Mahmut Yilmaz
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Publication number: 20170115352Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.Type: ApplicationFiled: October 27, 2016Publication date: April 27, 2017Inventors: Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Sailendra Chadalavda, Jonathon E. Colburn, Kevin Wilder, Mahmut Yilmaz