Patents by Inventor Karthikeyan Pillai

Karthikeyan Pillai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220115399
    Abstract: In certain embodiments, a method of fabricating a device includes forming, on a substrate, a layer stack of alternating layers of a first spin-on material and a second spin-on material. Each layer of the first spin-on material and the second spin-on material is formed by spin-on deposition. The method includes etching first openings through the layer stack and filling the first openings with a third material. The method includes etching second openings through the layer stack, removing the first spin-on material from the layer stack, and replacing the first spin-on material with a fourth material. The fourth material is a first metal-containing material.
    Type: Application
    Filed: September 10, 2021
    Publication date: April 14, 2022
    Inventors: Soo Doo Chae, Karthikeyan Pillai, Lior Huli, Na Young Bae, Hojin Kim
  • Patent number: 10734278
    Abstract: A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hirokazu Aizawa, Karthikeyan Pillai, Nicholas Joy, Kandabara Tapily
  • Publication number: 20190385906
    Abstract: A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Inventors: Hirokazu Aizawa, Karthikeyan Pillai, Nicholas Joy, Kandabara Tapily