Patents by Inventor Karthikeyan Ramamurthi
Karthikeyan Ramamurthi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11210025Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.Type: GrantFiled: December 23, 2019Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Aliasgar S. Madraswala, Purval S. Sule, Karthikeyan Ramamurthi
-
Publication number: 20200133579Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.Type: ApplicationFiled: December 23, 2019Publication date: April 30, 2020Inventors: Aliasgar S. Madraswala, Purval S. Sule, Karthikeyan Ramamurthi
-
Publication number: 20200090743Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.Type: ApplicationFiled: October 4, 2019Publication date: March 19, 2020Inventors: Aliasgar S. MADRASWALA, Bharat M. PATHAK, Binh N. NGO, Naveen VITTAL PRABHU, Karthikeyan RAMAMURTHI, Pranav KALAVADE
-
Patent number: 10514862Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.Type: GrantFiled: July 21, 2016Date of Patent: December 24, 2019Assignee: Micron Technology, Inc.Inventors: Aliasgar S. Madraswala, Purval S. Sule, Karthikeyan Ramamurthi
-
Patent number: 10438656Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.Type: GrantFiled: December 18, 2017Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Aliasgar S. Madraswala, Bharat M. Pathak, Binh N. Ngo, Naveen Vittal Prabhu, Karthikeyan Ramamurthi, Pranav Kalavade
-
Publication number: 20190043564Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.Type: ApplicationFiled: December 18, 2017Publication date: February 7, 2019Applicant: Intel CorporationInventors: ALIASGAR S. MADRASWALA, BHARAT M. PATHAK, BINH N. NGO, NAVEEN VITTAL PRABHU, KARTHIKEYAN RAMAMURTHI, PRANAV KALAVADE
-
Publication number: 20180024772Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.Type: ApplicationFiled: July 21, 2016Publication date: January 25, 2018Inventors: Aliasgar S. Madraswala, Purval S. Sule, Karthikeyan Ramamurthi
-
Patent number: 8069403Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.Type: GrantFiled: July 1, 2008Date of Patent: November 29, 2011Assignee: SanDisk Technologies Inc.Inventors: Omprakash Bisen, Karthikeyan Ramamurthi, Hima Bindu
-
Publication number: 20100005373Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.Type: ApplicationFiled: July 1, 2008Publication date: January 7, 2010Inventors: Omprakash Bisen, Karthikeyan Ramamurthi, Hima Bindu
-
Patent number: 7327605Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: GrantFiled: December 28, 2006Date of Patent: February 5, 2008Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher
-
Publication number: 20080008010Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: ApplicationFiled: December 28, 2006Publication date: January 10, 2008Inventors: Daniel Elmhurst, Karthikeyan Ramamurthi, Quan Ngo, Robert Melcher
-
Patent number: 7177186Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: GrantFiled: March 28, 2006Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher
-
Publication number: 20060193172Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: ApplicationFiled: March 28, 2006Publication date: August 31, 2006Inventors: Daniel Elmhurst, Karthikeyan Ramamurthi, Quan Ngo, Robert Melcher
-
Patent number: 7075822Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: GrantFiled: December 31, 2002Date of Patent: July 11, 2006Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher
-
Patent number: 7057934Abstract: A flash memory includes multi-level cells (MLC) that are programmed with a combination of coarse gate voltage steps and fine gate voltage steps. The multi-level cells include floating gate transistors that are programmed by modifying the threshold voltages of the floating gate transistors. Coarse gate voltage steps are used until the threshold voltage any of the transistors being programmed reaches a reference value, and fine steps are used thereafter.Type: GrantFiled: June 29, 2004Date of Patent: June 6, 2006Assignee: Intel CorporationInventors: Sreeram Krishnamachari, Karthikeyan Ramamurthi
-
Publication number: 20050286304Abstract: A flash memory is programmed with a combination of coarse gate voltage steps and fine gate voltage steps.Type: ApplicationFiled: June 29, 2004Publication date: December 29, 2005Inventors: Sreeram Krishnamachari, Karthikeyan Ramamurthi
-
Publication number: 20040128594Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher