Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.

Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

Abstract: Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.

Abstract: Methods and systems for recovering corrupted/degraded images using approximations obtained from an ensemble of multiple sparse models are disclosed. Sparse models may represent images parsimoniously using elementary patterns from a “dictionary” matrix. Various embodiments of the present disclosure involve simple and computationally efficient dictionary design approach along with low-complexity reconstruction procedure that may use a parallel-friendly table-lookup process. Multiple dictionaries in an ensemble model may be inferred sequentially using greedy forward-selection approach and can incorporate bagging/boosting strategies, taking into account application-specific degradation. Recovery performance obtained using the proposed approaches with image super resolution and compressive recovery can be comparable to or better than existing sparse modeling based approaches, at reduced computational complexity.

Abstract: Measuring the number of glomeruli in the entire, intact kidney using non-destructive techniques is of immense importance in studying several renal and systemic diseases. In particular, a recent Magnetic Resonance Imaging (MRI) technique, based on injection of a contrast agent, cationic ferritin, has been effective in identifying glomerular regions in the kidney. In various embodiments, a low-complexity, high accuracy method for obtaining the glomerular count from such kidney MRI images is described. This method employs a patch-based approach for identifying a low-dimensional embedding that enables the separation of glomeruli regions from the rest. By using only a few images marked by the expert for learning the model, the method provides an accurate estimate of the glomerular number for any kidney image obtained with the contrast agent. In addition, the implementation of our method shows that this method is near real-time, and can process about 5 images per second.

Abstract: A robust method to automatically segment and identify tumor regions in medical images is extremely valuable for clinical diagnosis and disease modeling. In various embodiments, an efficient algorithm uses sparse models in feature spaces to identify pixels belonging to tumorous regions. By fusing both intensity and spatial location information of the pixels, this technique can automatically localize tumor regions without user intervention. Using a few expert-segmented training images, a sparse coding-based classifier is learned. For a new test image, the sparse code obtained from every pixel is tested with the classifier to determine if it belongs to a tumor region. Particular embodiments also provide a highly accurate, low-complexity procedure for cases when the user can provide an initial estimate of the tumor in a test image.

Abstract: A robust method to automatically segment and identify tumor regions in medical images is extremely valuable for clinical diagnosis and disease modeling. In various embodiments, an efficient algorithm uses sparse models in feature spaces to identify pixels belonging to tumorous regions. By fusing both intensity and spatial location information of the pixels, this technique can automatically localize tumor regions without user intervention. Using a few expert-segmented training images, a sparse coding-based classifier is learned. For a new test image, the sparse code obtained from every pixel is tested with the classifier to determine if it belongs to a tumor region. Particular embodiments also provide a highly accurate, low-complexity procedure for cases when the user can provide an initial estimate of the tumor in a test image.

Abstract: Measuring the number of glomeruli in the entire, intact kidney using non-destructive techniques is of immense importance in studying several renal and systemic diseases. In particular, a recent Magnetic Resonance Imaging (MRI) technique, based on injection of a contrast agent, cationic ferritin, has been effective in identifying glomerular regions in the kidney. In various embodiments, a low-complexity, high accuracy method for obtaining the glomerular count from such kidney MRI images is described. This method employs a patch-based approach for identifying a low-dimensional embedding that enables the separation of glomeruli regions from the rest. By using only a few images marked by the expert for learning the model, the method provides an accurate estimate of the glomerular number for any kidney image obtained with the contrast agent. In addition, the implementation of our method shows that this method is near real-time, and can process about 5 images per second.

Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.

Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.

Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

Abstract: A flash memory includes multi-level cells (MLC) that are programmed with a combination of coarse gate voltage steps and fine gate voltage steps. The multi-level cells include floating gate transistors that are programmed by modifying the threshold voltages of the floating gate transistors. Coarse gate voltage steps are used until the threshold voltage any of the transistors being programmed reaches a reference value, and fine steps are used thereafter.