Abstract: An apparatus mountable on a wearer's wrist includes a housing having at front portion and an opposite a back portion. The back portion is wearably positionable in contact with the wearer's wrist. The apparatus includes a PPG circuit for generating a PPG signal. The PPG circuit includes a light source and a photosensor on the housing back portion. The PPG signal may be used to continuously determine the wearer's a pulse rate. The PPG signal may also be used in combination with an ECG signal to determine the wearer's instantaneous blood pressure. The ECG signal may also be used to determine the wear's heart rate. The ECG signal may be generated with an electrode mounted on the back of the housing and another electrode mounted on another portion of the housing, such as the back or one or more of the sides.

Abstract: A chopper-stabilized amplifier (20A) includes an amplifier (3), an input chopper (2A) having a first input (4) receiving an input signal (VIN+), an output (5) coupled to a first input of the amplifier, and a feedback resistor (9) coupled to an output (6) of the amplifier to couple a feedback signal (VFB+) to a second input of the amplifier (3). The input chopper operates in response to a chopping clock (CHOP_CLK). If the amplifier (3) is unacceptably close to a saturation condition, the chopping clock (CHOP_CLK) is disabled to reduce input leakage current (ILEAKAGE) of the chopper-stabilized amplifier.

Abstract: A chopper-stabilized amplifier (20A) includes an amplifier (3), an input chopper (2A) having a first input (4) receiving an input signal (VIN+), an output (5) coupled to a first input of the amplifier, and a feedback resistor (9) coupled to an output (6) of the amplifier to couple a feedback signal (VFB+) to a second input of the amplifier (3). The input chopper operates in response to a chopping clock (CHOP_CLK). If the amplifier (3) is unacceptably close to a saturation condition, the chopping clock (CHOP_CLK) is disabled to reduce input leakage current (ILEAKAGE) of the chopper-stabilized amplifier.

Abstract: Delta-sigma analog-to-digital converters (ADCs) and methods to calibrate methods to delta-sigma ADCs are disclosed. In one particular example, a delta-sigma ADC is described, including an n-bit feedback digital-to-analog converter (DAC) having a number of unit elements, and is configured to provide a feedback signal to a summing device, which generates a difference signal based on an analog input signal and the feedback signal. An n-bit ADC is included to generate an n-bit digital signal based on the difference signal. A dynamic element matching device selects one or more unit elements in the DAC based on the n-bit digital signal. A storage device, such as a memory, stores error coefficients corresponding to the plurality of unit elements. Finally, a digital corrector is included to receive the selection of unit elements, receive error coefficients corresponding to the selected unit elements, and adjust the n-bit digital signal based on the received error coefficients.

Abstract: The invention includes methods and systems for providing a multi-path common mode feedback loop in an amplifier system. Embodiments include techniques for dividing a common mode feedback current path to provide a slow common mode feedback current path and a fast common mode feedback current path. The slow and fast paths are configured for controlling common mode feedback current within a small bandwidth.

Abstract: The invention provides methods and systems useful for quickly and accurately sampling a switched capacitive load. Systems are disclosed in which the methods are implemented using an operational amplifier operably coupled to a pre-charge capacitor for storing an input charge. A sampling capacitor is also coupled to the operational amplifier and to the pre-charge capacitor for receiving and holding the input charge. The system is so configured for a coarse sampling phase and a fine sampling phase the to ensure that the sampling capacitor settles quickly to provides an output.

Abstract: The invention provides methods and systems useful for quickly and accurately sampling a switched capacitive load. Systems are disclosed in which the methods are implemented using an operational amplifier operably coupled to a pre-charge capacitor for storing an input charge. A sampling capacitor is also coupled to the operational amplifier and to the pre-charge capacitor for receiving and holding the input charge. The system is so configured for a coarse sampling phase and a fine sampling phase the to ensure that the sampling capacitor settles quickly to provides an output.

Abstract: The invention includes methods and systems for providing a multi-path common mode feedback loop in an amplifier system. Embodiments include techniques for dividing a common mode feedback current path to provide a slow common mode feedback current path and a fast common mode feedback current path. The slow and fast paths are configured for controlling common mode feedback current within a small bandwidth.

Abstract: A sigma-delta modulator disclosed herein provides a first order noise shaping of the errors associated with the multi bit DAC employing unit elements, without creating large in-band tones. The sigma-delta modulator includes a multi-bit ADC connected to receive a processed signal from a filter that performs first order noise shaping. Additionally, a feedback path, leading from the multi-bit ADC to a summer, includes at least one dynamic element matching algorithm logic block connected to a multi-bit DAC having a plurality of unit elements. The dynamic element matching algorithm logic block alternately generates a consecutive increment shift signal and a random shift signal at a predetermined or a random time interval for shifting the digital feedback signal by a random amount depending upon the amplitude and frequency of the analog input signal to provide a randomized rotated output to the DAC.

Abstract: A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.

Abstract: A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.