Patents by Inventor Karthisha Canagasaby

Karthisha Canagasaby has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pre-drivers for current-mode I/O drivers
    Patent number: 7245156
    Abstract: A pre-driver circuit includes a first stage to generate a first pre-driver signal and a second stage to generate a second pre-driver signal. The first and second stages are to generate the first and second pre-driver signals to cross at a point which reduces rise-and-fall mismatch in differential signal outputs from a current-mode driver.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Evelina F. Yeung, Karthisha Canagasaby, Sanjay Dabral
  • Equalizing a transmitter
    Publication number: 20070071083
    Abstract: In one embodiment, the present invention includes a method for associating a first plurality of current sources with a first tap coefficient and associating a second plurality of current sources with a second tap coefficient. A first plurality of output switches coupled to the first plurality of current sources is gated using the first tap coefficient and a second plurality of output switches coupled to the second plurality of current sources is gated using the second tap coefficient. In such manner, the first and second plurality of equalized current sources may be driven onto an interconnect. Other embodiments are described and claimed.
    Type: Application
    Filed: September 28, 2005
    Publication date: March 29, 2007
    Inventors: Karthisha Canagasaby, Muraleedhara Navada, Sanjay Dabral
  • Serial link apparatus, method, and system
    Publication number: 20070025492
    Abstract: A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.
    Type: Application
    Filed: June 30, 2005
    Publication date: February 1, 2007
    Inventors: Karthisha Canagasaby, Ken Drottar, David Dunning, Sanjay Dabral
  • Pre-drivers for current-mode I/O drivers
    Publication number: 20060220674
    Abstract: A pre-driver circuit includes a first stage to generate a first pre-driver signal and a second stage to generate a second pre-driver signal. The first and second stages are to generate the first and second pre-driver signals to cross at a point which reduces rise-and-fall mismatch in differential signal outputs from a current-mode driver.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Evelina Yeung, Karthisha Canagasaby, Sanjay Dabral
  • Low gain phase-locked loop circuit
    Patent number: 6977537
    Abstract: According to some embodiments, a low gain phase-locked loop circuit is provided.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: December 20, 2005
    Assignee: Intel Corporation
    Inventors: Santanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby
  • Low gain phase-locked loop circuit
    Publication number: 20040246057
    Abstract: According to some embodiments, a low gain phase-locked loop circuit is provided.
    Type: Application
    Filed: July 13, 2004
    Publication date: December 9, 2004
    Inventors: Santanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby
  • Low gain phase-locked loop circuit
    Patent number: 6788155
    Abstract: A low gain phase-locked loop circuit comprising a phase detector, a plurality of voltage controlled oscillators, wherein each voltage controlled oscillator is selectable to provide an output clock signal based at least in part on information generated by the phase detector; and a multiplexer to output a signal generated by one of the voltage controlled oscillators as the output clock signal based on a multi-bit selection control signal.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 7, 2004
    Assignee: Intel Corporation
    Inventors: Santanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby
  • Low gain phase-locked loop circuit
    Publication number: 20040124884
    Abstract: According to some embodiments, a low gain phase-locked loop circuit is provided.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Santanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby