Patents by Inventor Kartik Nanda

Kartik Nanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10097003
    Abstract: A system for managing delivery of electric power includes at least one source of electric power supplying an aggregate amount of available power and a plurality of electrical loads, each having a priority designation. There is a power management system electrically connected to the source of electrical power and to the plurality of electrical loads. The power management system monitors electrical power demanded by the electrical loads and the aggregate amount of available power of the at least one source of electric power. When the power management system determines that the aggregate demanded power exceeds the aggregate amount of available power, the power management system continues to provide power to each of said electrical loads but at a power level which is less than demanded to one or more of said plurality of electrical loads based on the priority designation of each of said electrical loads.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: October 9, 2018
    Inventor: Kartik Nanda
  • Patent number: 9698759
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: July 4, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 9563851
    Abstract: In an aspect, in general, a programmable computation device performs computations of an inference task specified by a plurality of variables and a plurality of factors, each factor being associated with a subset of the variables. The device includes one or more processing elements. Each processing element includes a first storage for a definition of a factor, a second storage for data associated with the inputs and/or outputs of at least some of the computations, and one or more computation units coupled to the first storage and the second storage for performing a succession of parts of the at least some of the computations that are associated with a factor, the succession of parts defined by data in the storage for the definition of the factor.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: February 7, 2017
    Assignee: Analog Devices, Inc.
    Inventors: Jeffrey Bernstein, Benjamin Vigoda, Kartik Nanda, Rishi Chaturvedi, David Hossack, William Peet, Andrew Schweitzer, Timothy Caputo
  • Publication number: 20170012429
    Abstract: A system for managing delivery of electric power includes at least one source of electric power supplying an aggregate amount of available power and a plurality of electrical loads, each having a priority designation. There is a power management system electrically connected to the source of electrical power and to the plurality of electrical loads. The power management system monitors electrical power demanded by the electrical loads and the aggregate amount of available power of the at least one source of electric power. When the power management system determines that the aggregate demanded power exceeds the aggregate amount of available power, the power management system continues to provide power to each of said electrical loads but at a power level which is less than demanded to one or more of said plurality of electrical loads based on the priority designation of each of said electrical loads.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 12, 2017
    Inventor: Kartik Nanda
  • Publication number: 20150381146
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Application
    Filed: May 5, 2014
    Publication date: December 31, 2015
    Applicant: Analog Devices, Inc.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 8717094
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: May 6, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 8576589
    Abstract: A power supply system and method includes a switch state controller that is operational to control a switching power converter during certain power loss conditions that cause conventional switch state controllers to have diminished or no functionality. In at least one embodiment, during certain power loss conditions, such as when an auxiliary power supply is in standby mode or when the switching power converter is not operating, a power supply for the switch state controller does not provide sufficient operating power to the switch state controller during certain power loss conditions. In at least one embodiment, during such power loss conditions power is generated for the switch state controller using sense input and/or sense output currents of the switching power converter to allow an integrated circuit (IC) switch state controller to generate a control signal to control a switch of the switching power converter.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 5, 2013
    Assignee: Cirrus Logic, Inc.
    Inventors: John L. Melanson, Karl Thompson, Kartik Nanda, Mauro Gaetano
  • Publication number: 20120306569
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicant: Analog Devices, Inc.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 7755525
    Abstract: A power control system includes a delta sigma modulator to generate output values for use in controlling a switching power converter. In at least one embodiment, the delta sigma modulator includes two ranges of available output values and a range of one or more unavailable intermediate output values, wherein the range of one or more unavailable intermediate output values represent a gap in available output values. Each unavailable intermediate output value represents an output value that is not generated by the delta sigma modulator. In at least one embodiment, the delta sigma modulator includes a quantizer output remapping module that remaps quantizer output values within the range of one or more unavailable intermediate output values of the delta sigma modulator to new output values within one of the ranges of available output values.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 13, 2010
    Assignee: Cirrus Logic, Inc.
    Inventors: Kartik Nanda, John L. Melanson
  • Patent number: 7750724
    Abstract: A temperature and process-stable magnetic field sensor bias current source provides improved performance in Hall effect sensor circuits. A switched-capacitor sensing element is used to sense either a reference current or the bias current directly. A current mirror may be used to generate the bias current from the reference current, and may include multiple current source transistors coupled through corresponding control transistors that are switched using a barrel shifter to reduce variations in the bias current due to process variation. The current mirror control may be provided via a chopper amplifier to reduce flicker noise and the current mirror control voltage may be held using a track/hold circuit during transitions of the chopper amplifier to further reduce noise due to the chopping action.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 6, 2010
    Assignee: Cirrus Logic, Inc.
    Inventors: Thirumalai Rengachari, Kartik Nanda, Larry L. Harris, John Paulos
  • Patent number: 7605723
    Abstract: Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: October 20, 2009
    Assignee: Cirrus Logic, Inc.
    Inventors: Kartik Nanda, Aryesh Amar
  • Publication number: 20090191837
    Abstract: A power control system includes a delta sigma modulator to generate output values for use in controlling a switching power converter. In at least one embodiment, the delta sigma modulator includes two ranges of available output values and a range of one or more unavailable intermediate output values, wherein the range of one or more unavailable intermediate output values represent a gap in available output values. Each unavailable intermediate output value represents an output value that is not generated by the delta sigma modulator. In at least one embodiment, the delta sigma modulator includes a quantizer output remapping module that remaps quantizer output values within the range of one or more unavailable intermediate output values of the delta sigma modulator to new output values within one of the ranges of available output values.
    Type: Application
    Filed: September 30, 2008
    Publication date: July 30, 2009
    Inventors: Kartik Nanda, John L. Melanson
  • Publication number: 20090189579
    Abstract: A power supply system and method includes a switch state controller that is operational to control a switching power converter during certain power loss conditions that cause conventional switch state controllers to have diminished or no functionality. In at least one embodiment, during certain power loss conditions, such as when an auxiliary power supply is in standby mode or when the switching power converter is not operating, a power supply for the switch state controller does not provide sufficient operating power to the switch state controller during certain power loss conditions. In at least one embodiment, during such power loss conditions power is generated for the switch state controller using sense input and/or sense output currents of the switching power converter to allow an integrated circuit (IC) switch state controller to generate a control signal to control a switch of the switching power converter.
    Type: Application
    Filed: June 30, 2008
    Publication date: July 30, 2009
    Inventors: John L. Melanson, Karl Thompson, Kartik Nanda, Mauro Gaetano
  • Publication number: 20090160535
    Abstract: A temperature and process-stable magnetic field sensor bias current source provides improved performance in Hall effect sensor circuits. A switched-capacitor sensing element is used to sense either a reference current or the bias current directly. A current mirror may be used to generate the bias current from the reference current, and may include multiple current source transistors coupled through corresponding control transistors that are switched using a barrel shifter to reduce variations in the bias current due to process variation. The current mirror control may be provided via a chopper amplifier to reduce flicker noise and the current mirror control voltage may be held using a track/hold circuit during transitions of the chopper amplifier to further reduce noise due to the chopping action.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Inventors: Thirumalai Rengachari, Kartik Nanda, Larry L. Harris, John Paulos
  • Patent number: 7456765
    Abstract: A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and a characteristic of an additional data clock signal to an operating mode of the data converter. In another embodiment, the mapping system maps measurements of the master clock frequency alone to a data converter operating mode. In a further embodiment, the measurement circuitry measures the master clock frequency of a master clock signal, which is received directly from a master clock signal source without a modification in the master clock frequency.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: November 25, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson, Kartik Nanda
  • Patent number: 7382300
    Abstract: A system-on-chip (SoC) integrated circuit including an interleaved delta-sigma analog to digital converter (ADC) provides for reduced noise in the ADC conversions. The ADC is operated intermittently and the balance of the digital circuits forming the system are halted while the conversions take place. The halted portion of the system may include an output low-pass filter of the ADC. The system may include a processor core or other logic having a clock frequency unrelated to the ADC modulator clock frequency that is not otherwise clock-managed to reduce noise induced in the converter output by the operation of the core or other logic.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: June 3, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Kartik Nanda, John L. Melanson, Timothy Thomas Rueger
  • Patent number: 7365667
    Abstract: A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: April 29, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Kartik Nanda, John L. Melanson
  • Patent number: 7352303
    Abstract: A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: April 1, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson, Kartik Nanda
  • Patent number: 7348813
    Abstract: A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: March 25, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Kartik Nanda, Aryesh Amar, Rahul Singh, Jerome E Johnston
  • Patent number: 7317411
    Abstract: A delta-sigma having quantizer code pattern detection controlled dither reduces the probability of “stuck” code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the pattern detection and dither control reduce the probability of a stuck code sequence at startup. A pattern detection circuit detects a sequence of unchanging quantizer output values and injects a signal at the quantizer input to cause the quantizer to change levels. The injected signal may be a dither signal that is increased in amplitude in response to the detection of unchanging code sequences and then decreased when the quantizer output changes.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: January 8, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Kartik Nanda, Timothy Thomas Rueger