Patents by Inventor Kartik V. Talsania

Kartik V. Talsania has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and device for computing incremental checksums
    Patent number: 6643821
    Abstract: A method and a computing system compute an incremental checksum corresponding to a data packet. The incremental checksum is computed within one processor cycle of a processor. A first register (102) stores first checksum information corresponding to a data packet. A second register (104) stores second checksum information corresponding to old information being deleted from the data packet. A third register (106) stores third checksum information corresponding to new information being added to the data packet. An incremental checksum circuit (100), electrically connected to the first register (102), to the second register (104), and to the third register (106), provides resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet. The resulting checksum information is selectively stored in the first register (102).
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: November 4, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Faraydon O. Karim, Kartik V. Talsania, Vincent E. Wass
  • Method and device for computing incremental checksums
    Publication number: 20020095642
    Abstract: A method and a computing system compute an incremental checksum corresponding to a data packet. The incremental checksum is computed within one processor cycle of a processor. A first register (102) stores first checksum information corresponding to a data packet. A second register (104) stores second checksum information corresponding to old information being deleted from the data packet. A third register (106) stores third checksum information corresponding to new information being added to the data packet. An incremental checksum circuit (100), electrically connected to the first register (102), to the second register (104), and to the third register (106), provides resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet. The resulting checksum information is selectively stored in the first register (102).
    Type: Application
    Filed: November 30, 2000
    Publication date: July 18, 2002
    Applicant: STMicroelectronics, Inc.
    Inventors: Faraydon O. Karim, Kartik V. Talsania, Vincent E. Wass