Patents by Inventor Karttikeya Shah

Karttikeya Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790689
    Abstract: In a general aspect, a charging apparatus can include a power converter circuit configured to supply, from an input voltage, charging power for charging a battery of an electronic device; and a control circuit configured to determine a charging current limit and a charging voltage of the power converter circuit for charging the battery. Determining the charging current limit and the charging voltage can include: setting the current limit of the power converter circuit to an initial charging current limit and setting the charging voltage to an initial charging voltage; determining whether the power converter circuit is operating in a current limit mode or a voltage limit mode; and iteratively modifying the current limit of the power converter circuit until the power converter circuit dithers between the current limit mode and the voltage limit mode.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 29, 2020
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Mukund Krishna, Karttikeya Shah, Alvin Fok
  • Patent number: 10291052
    Abstract: In accordance with an embodiment, a bypass charging circuit includes a pair of transistors having current carrying terminals commonly connected to form a node. An input of a comparator is coupled to the node through a switch and to a resistor. Another input terminal of the comparator is coupled for receiving a reference voltage. Optionally, a transistor may be connected to the bypass charging circuit. In accordance with another embodiment a method is provided in which bypass charging transistors are coupled to first input of a comparator in response to closing a switch. A voltage is generated at the first input of the comparator in response to closing the switch and the voltage is compared with a reference voltage. In response to the comparison, a status indicator signal is generated to indicate the presence of a low-impedance failure in one or both of the bypass charging transistors.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 14, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: James A. Meacham, II, Karttikeya Shah
  • Publication number: 20180145517
    Abstract: In a general aspect, a charging apparatus can include a power converter circuit configured to supply, from an input voltage, charging power for charging a battery of an electronic device; and a control circuit configured to determine a charging current limit and a charging voltage of the power converter circuit for charging the battery. Determining the charging current limit and the charging voltage can include: setting the current limit of the power converter circuit to an initial charging current limit and setting the charging voltage to an initial charging voltage; determining whether the power converter circuit is operating in a current limit mode or a voltage limit mode; and iteratively modifying the current limit of the power converter circuit until the power converter circuit dithers between the current limit mode and the voltage limit mode.
    Type: Application
    Filed: November 7, 2017
    Publication date: May 24, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Mukund KRISHNA, Karttikeya SHAH, Alvin FOK
  • Publication number: 20170346328
    Abstract: In accordance with an embodiment, a bypass charging circuit includes a pair of transistors having current carrying terminals commonly connected to form a node. An input of a comparator is coupled to the node through a switch and to a resistor. Another input terminal of the comparator is coupled for receiving a reference voltage. Optionally, a transistor may be connected to the bypass charging circuit. In accordance with another embodiment a method is provided in which bypass charging transistors are coupled to first input of a comparator in response to closing a switch. A voltage is generated at the first input of the comparator in response to closing the switch and the voltage is compared with a reference voltage. In response to the comparison, a status indicator signal is generated to indicate the presence of a low-impedance failure in one or both of the bypass charging transistors.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 30, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: James A. Meacham, II, Karttikeya Shah