Patents by Inventor Karumbu Meyyappan

Karumbu Meyyappan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230209759
    Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 29, 2023
    Inventors: Karumbu MEYYAPPAN, Kyle ARRINGTON, David CRAIG, Pooya TADAYON
  • Publication number: 20230197594
    Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes a processor package including at least one processor integrated circuit (IC); an interposer including electrically conductive interposer interconnect; a first liquid metal well array including multiple liquid metal wells arranged between the processor package and the interposer, wherein the first liquid metal well array is attached to a surface of the processor package and attached to a first surface of the interposer and the interposer interconnect; a printed circuit board (PCB) attached to a second surface of the interposer and the interposer interconnect; a second liquid metal well array including a first surface attached to the first surface of the interposer and the interposer interconnect; and a first companion component package attached to a second surface of the second liquid metal well array.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Karumbu Meyyappan, Jeffory L. Smalley, Gregorio Murtagian, Srikant Nekkanty, Eric J.M. Moret, Pooya Tadayon
  • Publication number: 20230197622
    Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Karumbu Meyyappan, Jeffory L, Smalley, Gregorio Murtagian, Srikant Nekkanty, Pooya Tadayon, Eric J.M. Moret, Bijoyraj Sahu
  • Publication number: 20230197621
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an integrated circuit (IC) package substrate including package interconnect and a first substrate surface; a processor IC attached to the first substrate surface and electrically connected to the package interconnect; a liquid metal well array including multiple liquid metal wells, a first array surface attached to the first substrate surface, and a second array surface; and a companion component to the processor IC attached to the second array surface of the liquid metal well array.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Karumbu Meyyappan, Jeffory L. Smalley, Gregorio Murtagian, Srikant Nekkanty, Eric J.M. Moret, Pooya Tadayon
  • Publication number: 20230187850
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a socket that includes one or more liquid metal filled reservoirs. In selected examples, the electronic devices and sockets include configurations to aid in reducing ingress of moisture.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Ziyin Lin, Aaron Michael Garelick, Karumbu Meyyappan, Gregorio Murtagian, Srikant Nekkanty, Taylor Rawlings, Jeffory L. Smalley, Pooya Tadayon, Dingying Xu
  • Publication number: 20230187337
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes liquid metal pathways that form one or more conduction pathway through one or more dielectric layers. In selected examples, the dielectric layers are resilient, which allows for flexibility of interconnect components.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Karumbu Meyyappan, Srikant Nekkanty, Gregorio Murtagian, Pooya Tadayon, Ziyin Lin, Eric J.M. Moret, Jeffory L. Smalley, Dingying Xu
  • Publication number: 20230185037
    Abstract: An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Inventors: Eric J. M. Moret, Pooya Tadayon, Karumbu Meyyappan, Paul J. Diglio
  • Patent number: 11622466
    Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Karumbu Meyyappan, Kyle Arrington, David Craig, Pooya Tadayon
  • Patent number: 11543454
    Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Paul J. Diglio, Pooya Tadayon, Karumbu Meyyappan
  • Publication number: 20210392774
    Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Karumbu MEYYAPPAN, Kyle ARRINGTON, David CRAIG, Pooya TADAYON
  • Publication number: 20200096567
    Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Paul J. Diglio, Pooya Tadayon, Karumbu Meyyappan
  • Patent number: 10109940
    Abstract: Embodiments herein relate to port frames and connectors for direct connections to integrated circuit packages. In various embodiments, a port frame to receive a connector and maintain a connection between the connector and a computer processor package may include a protrusion to provide stable attachment of the port frame to a bolster frame, a first wall, a second wall opposite the first wall, a first detent in the first wall, and a second detent in the second wall where the connector is to be received between the first wall and the second wall, and where the first detent is to receive a first locking protrusion extending from the connector and the second detent is to receive a second locking protrusion extending from the connector. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Thomas A. Boyd, Feifei Cheng, Donald T. Tran, Russell S. Aoki, Karumbu Meyyappan
  • Patent number: 10044115
    Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Donald T. Tran, Gregorio Murtagian, Kuang Liu, Srikant Nekkanty, Feroz Mohammad, Karumbu Meyyappan, Hong Xie, Russell S. Aoki, Gaurav Chawla
  • Publication number: 20180166807
    Abstract: Embodiments herein relate to port frames and connectors for direct connections to integrated circuit packages. In various embodiments, a port frame to receive a connector and maintain a connection between the connector and a computer processor package may include a protrusion to provide stable attachment of the port frame to a bolster frame, a first wall, a second wall opposite the first wall, a first detent in the first wall, and a second detent in the second wall where the connector is to be received between the first wall and the second wall, and where the first detent is to receive a first locking protrusion extending from the connector and the second detent is to receive a second locking protrusion extending from the connector. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 14, 2018
    Inventors: THOMAS A. BOYD, FEIFEI CHENG, DONALD T. TRAN, RUSSELL S. AOKI, KARUMBU MEYYAPPAN
  • Patent number: 9859636
    Abstract: An example apparatus for connecting linear edge cards includes a housing to hold at least one set of conductive contacts facing perpendicularly towards a mating plane. The apparatus further includes an activator bar coupled to the housing, the activator bar to hold two parts of the housing apart via two opposing normal forces. The apparatus also includes a contact load spring coupled to the housing, the contact load spring to apply two forces parallel to the direction of the conductive contacts and against the two opposing normal forces of the activator bar. The apparatus further includes an ejector spring coupled to the contact load spring and the activator bar. The ejector spring is to apply a force perpendicular to the two opposing normal forces of the activator bar and in a direction of an opening of the housing.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Thomas A. Boyd, Jeffory L. Smalley, Russell S. Aoki, Karumbu Meyyappan
  • Publication number: 20170187134
    Abstract: An example apparatus for connecting linear edge cards includes a housing to hold at least one set of conductive contacts facing perpendicularly towards a mating plane. The apparatus further includes an activator bar coupled to the housing, the activator bar to hold two parts of the housing apart via two opposing normal forces. The apparatus also includes a contact load spring coupled to the housing, the contact load spring to apply two forces parallel to the direction of the conductive contacts and against the two opposing normal forces of the activator bar. The apparatus further includes an ejector spring coupled to the contact load spring and the activator bar. The ejector spring is to apply a force perpendicular to the two opposing normal forces of the activator bar and in a direction of an opening of the housing.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Applicant: INTEL CORPORATION
    Inventors: Thomas A. Boyd, Jeffory L. Smalley, Russell S. Aoki, Karumbu Meyyappan
  • Publication number: 20170187147
    Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Donald T. Tran, Gregorio Murtagian, Kuang Liu, Srikant Nekkanty, Feroz Mohammad, Karumbu Meyyappan, Hong Xie, Russell S. Aoki, Gaurav Chawla