Patents by Inventor Karun Sharma

Karun Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10452807
    Abstract: Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 22, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Karun Sharma, Nikhil Garg, Juno Jui-Chuan Lin, Subhashis Mandal, Chandra Prakash Manglani, Kanaka Raju Gorle, Henry Yu
  • Patent number: 10452806
    Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to automatically generate a track pattern for an integrated circuit design that satisfies both design constraints and user inputs. Various alternatives for identifying starting points in the design for automatically generating track patterns are possible.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 22, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sabra Rossman, Gary Matsunami, Karun Sharma, Steven Riley, Joshua A. Baudhuin
  • Patent number: 10402530
    Abstract: Disclosed are techniques for implementing placement using row templates for an electronic design using row templates. These techniques identify or create a row region in a layout of an electronic design. A row template is applied to the row region to create one or more placement rows in the row region. One or more layout circuit components may then be placed into one or more rows or at one or more locations to create a legal placement layout by guiding placement of the one or more layout circuit components with the row template.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Karun Sharma, Yu Liu, Subhashis Mandal, Kanaka Raju Gorle, Jeff Taraldson
  • Patent number: 10346573
    Abstract: An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are re-processed for simulation. The unaffected partitions do not necessarily need to be reprocessed.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 9, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Karun Sharma, Roland Ruehl, Arnold Ginetti, Srihari Sampath
  • Patent number: 10296695
    Abstract: Methods and systems for implementing track pattern for electronic designs are disclosed. The method identifies a first track in a design and viable implementing options for the first track. When adding a second track to the track pattern, the method determines whether the second track corresponds to the viable implementing options for the track. The second track is inserted to the track pattern and situated immediately adjacent to the first track if the second track is determined to correspond to a viable implementing option for the first track. One or more intermediate tracks may be inserted immediately adjacent to the first track before inserting the second track to produce a legal track pattern. Tracks may be removed from a track pattern. One or more intermediate tracks may be inserted into the space occupied by a track being removed to ensure track pattern's compliance with design rules after the track removal.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: May 21, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinnie Lee, Jeffrey Markham, Roland Ruehl, Karun Sharma
  • Patent number: 10255402
    Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to snap instances to a set of such tracks such that all pins/shapes in the instance result in valid locations. In some embodiments, the methodology further includes creating a geometric representation of the tracks to assist in the quick identification of matching tracks.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 9, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sabra Rossman, Karun Sharma, Juno Lin
  • Patent number: 9904756
    Abstract: Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more lateral fill shapes along one or more routing tracks of a legal track pattern while automatically complying with the design rules, and perform post-lateral fill or post-layout operations to improve the layout and to prepare the layout for manufacturing.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: February 27, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Roland Ruehl, Alexandre Arkhipov, Giles V. Powell, Karun Sharma
  • Patent number: 9754072
    Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 5, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami
  • Patent number: 9659138
    Abstract: Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal track pattern is generated by arranging multiple tracks in an order and further by associating the first width with the first track in the custom, legal track pattern. The layout may then be further modified by guiding the insertion of one or more additional shapes with the custom, legal track pattern.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 23, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Giles V. Powell, Alexandre Arkhipov, Roland Ruehl, Karun Sharma
  • Patent number: 9652579
    Abstract: Disclosed are techniques for implementing parallel fills for electronic designs These techniques identify a shape and one or more neighboring shapes of the shape by searching design data of a region of a layout of an electronic design, classify the shape and the one or more neighboring shapes by examining respective characteristics of and to categorize the shape and the one or more neighboring shapes into one or more classes, implement one or more parallel fill shapes for at least one shape of the shape and the one or more neighboring shapes by aggregating the one or more parallel fill shapes to the at least one shape based in part or in whole upon the one or more classes while automatically satisfying one or more design rules, and perform one or more post-layout operations on the layout including the one or more parallel fill shapes.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 16, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alexandre Arkhipov, Giles V. Powell, Roland Ruehl, Karun Sharma
  • Patent number: 9563737
    Abstract: Methods and systems for checking or verifying shapes in electronic designs are disclosed. The method identifies a dictionary (if pre-existing) or determining the dictionary by creating the dictionary and reduces dimensionality of design data by using a sliced line. Shapes are transformed into sliced line segments along the sliced line. Dictionary entries for shapes are associated with corresponding sliced line segments, and the design is checked or verified using the sliced line segments and the associated dictionary entries rather than using two-dimensional shapes or geometric data. Sliced line segments may be further partitioned or merged. Non-conforming shapes corresponding to no tracks of track patterns are identified and determined whether violations of design rules or requirements may be resolved by one or more other shapes using the corresponding sliced line segments.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 7, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alexandre Arkhipov, Jeffrey Markham, Karun Sharma
  • Patent number: 9396301
    Abstract: Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy pins or ordering of pin connections in implementing the interconnection to satisfy certain design rules. The lengths of some wire segments of the interconnection may be further adjusted to satisfy certain design rules. Compaction may be performed to have two wire segments share the same track while the lengths or widths of one or both wire segments may be further modified to ensure design rule compliance.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 19, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinnie Lee, Jeffrey Markham, Roland Ruehl, Karun Sharma
  • Patent number: 9384317
    Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 5, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami
  • Patent number: 9372955
    Abstract: Methods and systems for implementing repetitive track patterns for electronic designs are disclosed. The method determines a track pattern within a period and repeats the track pattern for a number of times to form repetitive track patterns. Compliance with photomask designation design rules and track pattern design rules by both the track pattern and the repetitive track patterns is maintained by adding one or more intermediate tracks. A track may be added or removed from the track pattern or replaced by another track associated with a different width by using one or more intermediate tracks. The method may validate a period and replace an invalid period with a valid period. During the identification of the tracks in a track pattern for constructing repetitive track patterns, the method also forward predicts a predetermined number of tracks or predicts one or more tracks for a predetermined distance.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: June 21, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinnie Lee, Jeffrey Markham, Roland Ruehl, Karun Sharma
  • Patent number: 9326825
    Abstract: A patient mountable robot includes a four link mechanism, three actuators, and a first robot base. The mechanism includes four links that form a closed loop structure. The four links include a base link that includes a spherical joint. The mechanism provides two rotational degrees of freedom about the spherical joint for a needle that is configured to pass through the spherical joint. A first actuator is attached to the mechanism and moves the mechanism to provide the first of the two rotational degrees of freedom. A second actuator is attached to the mechanism and moves the mechanism to provide the second of the two rotational degrees of freedom. The base link of the mechanism passes through the first robot base. A third actuator is attached to the first robot base and linearly translates the base link so that a translational degree of freedom is provided for the needle.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 3, 2016
    Assignee: Children's National Medical Center
    Inventors: Kevin Cleary, Reza Monfaredi, Raymond Sze, Karun Sharma, Nabile Safdar, Reza Seifabadi
  • Patent number: 9256708
    Abstract: Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments can be rendered as a geometric shape in the IC design layout. Based on the marker, the method generates several solutions each of which will cause the set of shapes to meet the design rule when the solution is applied to the set. Each solution requires moving at least one edge of a shape in the set of shapes.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: February 9, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventor: Karun Sharma
  • Publication number: 20140371584
    Abstract: A patient mountable robot includes a four link mechanism, three actuators, and a first robot base. The mechanism includes four links that form a closed loop structure. The four links include a base link that includes a spherical joint. The mechanism provides two rotational degrees of freedom about the spherical joint for a needle that is configured to pass through the spherical joint. A first actuator is attached to the mechanism and moves the mechanism to provide the first of the two rotational degrees of freedom. A second actuator is attached to the mechanism and moves the mechanism to provide the second of the two rotational degrees of freedom. The base link of the mechanism passes through the first robot base. A third actuator is attached to the first robot base and linearly translates the base link so that a translational degree of freedom is provided for the needle.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Applicant: CHILDREN'S NATIONAL MEDICAL CENTER
    Inventors: Kevin CLEARY, Reza MONFAREDI, Raymond SZE, Karun SHARMA, Nabile SAFDAR, Reza SEIFABADI
  • Patent number: 8473874
    Abstract: A method for automatically generating and prioritizing several design solutions that resolve a double patterning (DP) loop violation in an IC design layout. The method of some embodiments receives a DP loop violation marker and identifies pairs of edges of shapes that form a double patterning loop based on the DP loop violation marker. For each pair of edges that violates the design rule, the method generates one or more design solutions. Each design solution moves a single edge or both edges to resolve the violation. The method of some embodiments computes the cost of applying each design solution to the IC design layout and prioritizes the generated solutions for all the identified pairs of edges based on the computed cost for each solution. The method in some embodiments then selects a solution from the prioritized solutions and applies the selected solution to the design layout.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: June 25, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Karun Sharma, Min Cao, Roland Ruehl
  • Publication number: 20120124536
    Abstract: Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments can be rendered as a geometric shape in the IC design layout. Based on the marker, the method generates several solutions each of which will cause the set of shapes to meet the design rule when the solution is applied to the set. Each solution requires moving at least one edge of a shape in the set of shapes.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventor: Karun Sharma