Patents by Inventor Karunakara Kotary
Karunakara Kotary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210303692Abstract: An apparatus to implement an IP independent secure firmware load into an IP agent without a ROM to establish hardware root of trust is disclosed.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Vinupama Godavarthi, Andrzej Mialkowski, Kar Leong Wong, Aditya Katragada, Maciej Kusio, Prashant Dewan, Karunakara Kotary
-
Publication number: 20210303691Abstract: An apparatus to implement an IP independent firmware load is disclosed. The apparatus includes a plurality of agents, a plurality of agents, at least one agent including a memory to store firmware to be executed by the agent to perform a function associated with the agent and a register to store enumeration data for the firmware load mechanism of the IP, and a processor to initiate an enumeration process to read the enumeration data from the register of the at least one agent, make a decision based on that data to retrieve a firmware module from a storage device, verify the firmware module, and load the firmware module into the memory of the at least one agent.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Prashant Dewan, Karunakara Kotary, Nivedita Aggarwal, Vinupama Godavarthi, Aditya Katragada, Mohamed Haniffa, Tung Lun Loo
-
Publication number: 20210124594Abstract: An apparatus and method are provided which take advantage of heterogeneous compute capability to dynamically pick the best operating core for BIOS power-up flows and sleep exit flows (e.g., S3, S4, and/or S5). The selection of the BSP is moved to an early power-up time instead of a fixed hardware selection at any time. For maximum boot performance, the system selects the fastest capable core as the BSP at an early power-up time. In addition, for maximum power saving, the system selects the most power efficient core as the BSP. Processor or switching for selecting the BSP happens during the boot-up as well as power-up flows (e.g., S3, S4, and/or S5 flows).Type: ApplicationFiled: October 16, 2020Publication date: April 29, 2021Applicant: Intel CorporationInventors: Pannerkumar Rajagopal, Karunakara Kotary, Sean Dardis
-
Publication number: 20210110043Abstract: An apparatus to facilitate a computer system platform boot is disclosed. The apparatus comprises a system on chip (SOC), including a cache memory, a storage device to store platform firmware including boot code, a security controller to load the boot code into the cache during a platform reset and a processor to execute the boot code from the cache memory to initiate the SOC.Type: ApplicationFiled: December 23, 2020Publication date: April 15, 2021Applicant: Intel CorporationInventors: Michael Berger, Anoop Mukker, Karunakara Kotary, Nivedita Aggarwal, Udy Hershkovitz, Arijit Chattopadhyay, Jabeena B. Gaibusab, Christopher J. Lake
-
Publication number: 20210109824Abstract: An apparatus to facilitate data resiliency in a computer system platform is disclosed.Type: ApplicationFiled: December 23, 2020Publication date: April 15, 2021Applicant: Intel CorporationInventors: Karunakara Kotary, Prashant Dewan, Vincent Zimmer, Rajesh Poornachandran
-
Publication number: 20210096840Abstract: Systems, apparatuses and methods may provide for technology that assumes, by a root of trust located in a trusted region of a system on chip (SOC), control over a reset of the SOC and conducting, by the root of trust, an authentication of an update package in response to an update condition. The root of trust technology may also apply the update package to firmware located in non-volatile memory (NVM) associated with a microcontroller of the SOC if the authentication is successful.Type: ApplicationFiled: August 10, 2020Publication date: April 1, 2021Inventors: Karunakara Kotary, Michael Kubacki, Sean Dardis
-
Publication number: 20210026649Abstract: Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.Type: ApplicationFiled: September 22, 2020Publication date: January 28, 2021Inventors: Karunakara Kotary, Pannerkumar Rajagopal, Satish Muthiyalu, Rajesh Poornachandran
-
Publication number: 20200410084Abstract: In some examples, an apparatus to authenticate a battery includes a battery voltage monitor to monitor a voltage of the battery. The apparatus to authenticate the battery also includes a voltage source regulator to filter the voltage of the battery and provide the filtered voltage to turn on circuitry to be used to authenticate the battery.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: INTEL CORPORATIONInventors: Sagar C. Pawar, Panner Kumar, Karunakara Kotary, Ovais F. Pir
-
Patent number: 10802998Abstract: Technologies for processor core soft-offlining include a computing device having a processor with multiple processor cores. On boot, an operating system queries a firmware interface to retrieve a potential offline set of processor cores. The operating system prevents the processor cores of the potential offline set from receiving device interrupts. The computing device detects a platform management event from the firmware interface and, in response to the platform management event, queries the firmware interface to determine a requested offline set of processor cores. Each of the processor cores in the requested offline set is included in the potential offline set. The computing device brings the processor cores of the requested offline set into a low-power state, and then the computing device may start performing a platform management operation. The platform management event may include a memory hot-plug event or a specialized workload event. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2016Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Karunakara Kotary, Gaurav Khanna, Abhinav R. Karhu
-
Publication number: 20200285403Abstract: An apparatus to facilitate memory map security in a system on chip (SOC), comprising is disclosed. The apparatus includes a micro controller to receive a request to grant a host device access to a memory device and perform an alias checking process to verify accuracy of a memory map of the memory device.Type: ApplicationFiled: March 27, 2020Publication date: September 10, 2020Applicant: Intel CorporationInventors: Karunakara Kotary, Pannerkumar Rajagopal, Sahil Dureja, Mohamed Haniffa, Prashant Dewan
-
Patent number: 10740084Abstract: Systems, apparatuses and methods may provide for technology that assumes, by a root of trust located in a trusted region of a system on chip (SOC), control over a reset of the SOC and conducting, by the root of trust, an authentication of an update package in response to an update condition. The root of trust technology may also apply the update package to firmware located in non-volatile memory (NVM) associated with a microcontroller of the SOC if the authentication is successful.Type: GrantFiled: August 16, 2018Date of Patent: August 11, 2020Assignee: Intel CorporationInventors: Karunakara Kotary, Michael Kubacki, Sean Dardis
-
Publication number: 20200225994Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Applicant: Intel CorporationInventors: Pannerkumar Rajagopal, Murali R. Iyengar, Karunakara Kotary, Ovais Pir, Sagar C. Pawar, Prakash Pillai, Raghavendra N., Aneesh A. Tuljapurkar
-
Publication number: 20200226260Abstract: An apparatus to facilitate firmware resiliency in a computer system platform is disclosed. The apparatus comprises a first non-volatile memory to store primary firmware for a computer system platform, a second non-volatile memory to store a firmware copy of the primary firmware and a resiliency hardware, coupled to the first non-volatile memory via the system fabric, to detect unauthorized access to the primary firmware and restore the primary firmware stored in the first non-volatile memory with the firmware copy.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Applicant: Intel CorporationInventors: Nivedita Aggarwal, Anoop Mukker, Michael Berger, Karunakara Kotary, Arijit Chattopadhyay, Rajesh Poornachandran
-
Publication number: 20200226028Abstract: Systems, apparatuses and methods may provide for technology that conducts a first copy of firmware data from a first partition in a storage device to a second partition in the storage device, detects a recovery condition with respect to the firmware data in the first partition, and automatically conducts a second copy of the firmware data from the second partition to the first partition in response to the recovery condition. In one example, the firmware data defines one or more settings for firmware code.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Karunakara Kotary, Sean Dardis, Michael Kubacki
-
Patent number: 10642665Abstract: Particular embodiments described herein provide for an electronic device that can receive data from an operating system in an electronic device, where the data is related to hardware that is in communication with the electronic device through a multimodal interface and communicate the data and/or related data to a local policy manager, where the local policy manager is in communication with the multimodal interface. The multimodal interface can be configured to support power transfers, directionality, and multiple input/output (I/O) protocols on the same interface.Type: GrantFiled: March 21, 2016Date of Patent: May 5, 2020Assignee: Intel CorporationInventors: Peter S. Adamson, Nivedita Aggarwal, Karunakara Kotary, Abdul Rahman Ismail, Tin-Cheung Kung, David T. Hines, Chia-Hung Sophia Kuo, Ajay V. Bhatt, Karthi R. Vadivelu, Prashant Sethi
-
Patent number: 10592254Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.Type: GrantFiled: September 5, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Rajesh Poornachandran, Vincent J. Zimmer, Karunakara Kotary, Venkatesh Ramamurthy, Pralhad M. Madhavi
-
Patent number: 10585721Abstract: Particular embodiments described herein provide for an electronic device that can receive data from an operating system in an electronic device, where the data is related to hardware that is in communication with the electronic device through a multimodal interface and communicate the data and/or related data to a local policy manager, where the local policy manager is in communication with the multimodal interface. The multimodal interface can be configured to support power transfers, directionality, and multiple input/output (I/O) protocols on the same interface.Type: GrantFiled: March 21, 2016Date of Patent: March 10, 2020Assignee: Intel CorporationInventors: Peter S. Adamson, Nivedita Aggarwal, Karunakara Kotary, Abdul Rahman Ismail, Tin-Cheung Kung, David T. Hines, Chia-Hung Sophia Kuo, Ajay V. Bhatt, Karthi R. Vadivelu, Prashant Sethi
-
Patent number: 10552613Abstract: A computing device that implements a secure and transparent firmware update process is provided. The computing device includes a secure memory area and a secure device that separately executes firmware updates in parallel with other processes executed by a CPU. The secure memory area may be allocated by the CPU and/or a memory controller using any of a variety of memory protection techniques. System software executed by the CPU receives update firmware requests from a trusted source, stores a firmware payload included in these requests in the secure memory area, and executes the next scheduled process. Firmware executed by the secure device retrieves the firmware payload from the secure memory area, authenticates the firmware payload, and applies the firmware payload to a firmware storage device. The secure device performs these acts transparently from the point of view of the CPU, these avoiding consumption of resources of the CPU.Type: GrantFiled: September 26, 2017Date of Patent: February 4, 2020Assignee: INTEL CORPORATIONInventors: Krishnakumar Narasimhan, Sudhakar Otturu, Karunakara Kotary, Vincent J. Zimmer
-
Publication number: 20190325139Abstract: A system comprising a controller to operate in an out of band fashion with respect to a central processing unit, the controller comprising a memory, and a processing element to request a firmware module from a computing system over a network, and cause the firmware module to be communicated to a storage controller for installation on a storage device.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Applicant: Intel CorporationInventors: Prashant Dewan, Karunakara Kotary
-
Publication number: 20190318097Abstract: There is disclosed in one example, a system-on-a-chip (SoC), including: a processor core; a fabric; an intellectual property (IP) block communicatively coupled to the processor core via the fabric, the IP block having a microcontroller configured to provide a microcontroller architecture; a firmware load interface configured to provide a standardized hardware interface to the microcontroller architecture, wherein the standardized hardware interface provides an architecture-agnostic mechanism to securely load a firmware to the intellectual property block; and logic to provide a loader to load a firmware to the IP block via the firmware load interface.Type: ApplicationFiled: June 28, 2019Publication date: October 17, 2019Inventors: Aditya Katragada, Prashant Dewan, Karunakara Kotary, Vinupama Godavarthi, Kumar Dwarakanath, Alex Izbinsky, Purushottam Goel