Abstract: An apparatus having a memory and a controller is disclosed. The memory may have a write head and sectors in tracks. The controller may have a sector map and a translation map and may be configured to (i) receive a write command having a logical block address and a range value, (ii) examine the sector map to find a sector sequence (a) marked free, (b) about to reach the write head and (c) at least as long as the range value, (iii) write new data in the sector sequence, (iv) update the translation map to associate the logical block address of the write command with a physical address of the written sectors and (v) update the sector map according to the sectors written. Each entry in the sector map generally corresponds to a respective sector and indicates whether the respective sector contains valid data or is free.

Abstract: An apparatus having a memory and a controller is disclosed. The memory may have a write head and sectors in tracks. The controller may have a sector map and a translation map and may be configured to (i) receive a write command having a logical block address and a range value, (ii) examine the sector map to find a sector sequence (a) marked free, (b) about to reach the write head and (c) at least as long as the range value, (iii) write new data in the sector sequence, (iv) update the translation map to associate the logical block address of the write command with a physical address of the written sectors and (v) update the sector map according to the sectors written. Each entry in the sector map generally corresponds to a respective sector and indicates whether the respective sector contains valid data or is free.