Abstract: A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, initiate calibration of the master device to send commands over the CA bus in the second swing mode, and to send a second command over the CA bus via the pins while in the second swing mode.

Abstract: A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, initiate calibration of the master device to send commands over the CA bus in the second swing mode, and to send a second command over the CA bus via the pins while in the second swing mode.

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source thaws multiple current levels in the single-ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination.

Abstract: A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source thaws multiple current levels in the single-ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination.