Abstract: A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter.

Abstract: A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter.