Abstract: A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.

Abstract: A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is discontinued and the final polishing is performed using the embedded small abrasive particles. Using this method dishing has been reduced considerably, and has enabled the fabrication of a Damascene metal gate NMOSFET fabricated with Atomic Layer Deposition (ALD).

Abstract: A method of manufacturing a planarized semiconductor wafer in which a semiconductor wafer is provided with a chemical-mechanical polishing stop layer deposited thereon. A photoresist layer is processed and used to form a patterned chemical-mechanical polishing stop layer and shallow trenches. A shallow trench isolation material is then grown on the chemical-mechanical polishing stop layer and in the shallow trenches, and is chemical-mechanical polished to the chemical-mechanical polishing stop layer.

Abstract: A memory includes a semiconductor substrate and a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited and formed. A doped wordline spacer layer is deposited and a doped wordline spacer is formed adjacent to the wordline.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer.

Abstract: A manufacturing method for a memory and a memory made thereby includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited and formed. A doped wordline spacer layer is deposited and a doped wordline spacer is formed adjacent to the wordline.

Abstract: A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.

Abstract: A method is provided for manufacturing a MirrorBit® Flash memory with high conductivity bitlines and shallow trench isolation integration. A hard mask is formed over a substrate and used to form a core trench and a shallow trench isolation (STI) trench. The trenches are filled with an insulating material in an STI fill process. A core mask is formed over the STI trenches and exposing the core trenches. The insulating material is removed from the core trenches and the core and hard mask are removed. A doped bitline material is deposited on the surface of the semiconductor, which fills the core trench. The surface of the semiconductor is planarized, inlaying insulating material and doped bitline material in the trenches. A thermal anneal causes the dopant diffusion from the doped bitline material into the substrate to form the high conductivity bitlines.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation. The organic additive-containing slurry cain be utilized throughout the entire polish time. Alternatively, a slurry not containing the organic additive can be utilized for a first portion of the polish, and a slurry containing the organic additive or a polishing solution containing the organic additive can be utilized for a second portion of the polish.

Abstract: A manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a grooved polyurethane polish pad, a very thin barrier layer may be used without the conductor core and dielectric layer being subject to erosion and the conductor core being subject to dishing.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation. The organic additive-containing slurry can be utilized throughout the entire polish time. Alternatively, a slurry not containing the organic additive can be utilized for a first portion of the polish, and a slurry containing the organic additive or a polishing solution containing the organic additive can be utilized for a second portion of the polish.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a grooved polyurethane polish pad, a very thin barrier layer may be used without the conductor core and dielectric layer being subject to erosion and the conductor core being subject to dishing.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a fixed abrasive polish pad, a very thin barrier layer may be used without the conductor core and the dielectric layer being subject to erosion or dishing.

Abstract: A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor wafer and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and a conductor core is deposited to fill the channel opening over the barrier layer. The semiconductor wafer is then subjected to chemical-mechanical polishing using a differential pressure between the center of the semiconductor wafer and its periphery.

Abstract: A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and conductor core is deposited to fill the channel opening over the barrier layer. By using a polishing solution having a dielectric protective characteristic, chemical-mechanical polishing of the conductor core and the barrier layer with the surface of the dielectric layer stops at the surface of the dielectric layer after planarization.

Abstract: The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining.

Abstract: A polishing pad is provided for chemical-mechanical polishing a dielectric layer in a multilevel semiconductor device. Embodiments include providing a polishing pad comprising a plurality of raised elements thereon and mechanically polishing a highly porous dielectric layer to form a planarized interlevel dielectric layer.

Abstract: A method of planarizing a copper containing conductive layer of a semiconductor wafer forms a blanketing copper containing layer within and upon a patterned substrate layer. Chemical mechanical polish (CMP) planarizing is performed on the copper containing layer at a relatively fast rate of removal until most of the layer is removed. The remaining portion of the layer is then CMP planarized at a second rate of removal, which is slower than the first rate of removal, until the copper containing layer is substantially completely removed and a barrier layer underlying the copper containing layer is reached. The multiple phase planarization of the copper containing layer avoids excessive dishing and pattern erosion while maintaining high throughput and uniform removal.