Patents by Inventor Kashyap Mohan

Kashyap Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222310
    Abstract: In examples, a semiconductor package comprises a substrate having multiple conductive layers coupled to bond pads at a surface of the substrate. The package includes a semiconductor die including a device side facing the substrate, the device side having first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region. The package also includes conductive members coupled to the bond pads of the substrate, in direct physical contact with the second circuitry region, and not in direct physical contact with the first circuitry region. The package further comprises a first support member coupled to the device side of the semiconductor die and extending toward the substrate and not touching the substrate or a second support member coupled to the substrate.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Gregory OSTROWICKI, Amit NANGIA, Kashyap MOHAN
  • Publication number: 20240145419
    Abstract: An example method includes placing a semiconductor die on a bonding surface of metal substrate. The die includes metal pillars extending from a surface of the die aligned with respective bonding locations on the bonding surface of the substrate. The pillars and the substrate can be formed of a common type of metal. The method also includes controlling a laser to emit laser light to heat the substrate at respective bonding locations to bond the metal pillars with the substrate at the respective bonding locations.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventors: Daiki KOMATSU, Kashyap MOHAN
  • Patent number: 11864471
    Abstract: A described example includes: a semiconductor die including a Hall sensor arranged in a first plane that is parallel to a device side surface of the semiconductor die; a passivated magnetic concentrator including a magnetic alloy layer formed over the device side surface of the semiconductor die, the upper surface of the magnetic alloy layer covered by a layer of polymer material; a backside surface of the semiconductor die opposite the device side surface mounted to a die side surface of a die pad on a package substrate, the semiconductor die having bond pads on the device side surface spaced from the magnetic concentrator; electrical connections coupling the bond pads of the semiconductor die to leads of the package substrate; and mold compound covering the magnetic concentrator, the semiconductor die, the electrical connections, a portion of the leads, and the die side surface of the die pad.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Rafael Jose Lizares Guevara, Dok Won Lee, Kashyap Mohan
  • Publication number: 20230317662
    Abstract: An electronic device includes a substrate, a semiconductor die, and a molded package structure that encloses a portion of the semiconductor die and extends to a portion of the substrate. A sensor surface extends along a side of the semiconductor die, and conductive terminals extend outward from the side and have ends soldered to conductive features of the substrate. The side of the semiconductor die is spaced apart from the substrate and the conductive terminals forming a cage structure that laterally surrounds the sensor surface. The molded package structure has a cavity that extends between the sensor surface and the substrate, and the cavity extends in an interior of a cage structure formed by the conductive terminals.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Rafael Jose Guevara, Laura May Antionette Dela Paz Clemente, Amin Sijelmassi, Kashyap Mohan
  • Publication number: 20230274993
    Abstract: One example includes a method for fabricating an integrated circuit (IC) device. The method includes fabricating a semiconductor die comprising an IC. The method also includes patterning a film over a portion of the first surface of the semiconductor die. The method also includes attaching a second surface of the semiconductor die opposite the first surface to a substrate. The method further includes depositing molding material over the semiconductor die to cover at least the first surface of the semiconductor die.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Inventors: Anindya PODDAR, Amin SIJELMASSI, Hau NGUYEN, Kashyap MOHAN
  • Publication number: 20230135922
    Abstract: A described example includes: a semiconductor die including a Hall sensor arranged in a first plane that is parallel to a device side surface of the semiconductor die; a passivated magnetic concentrator including a magnetic alloy layer formed over the device side surface of the semiconductor die, the upper surface of the magnetic alloy layer covered by a layer of polymer material; a backside surface of the semiconductor die opposite the device side surface mounted to a die side surface of a die pad on a package substrate, the semiconductor die having bond pads on the device side surface spaced from the magnetic concentrator; electrical connections coupling the bond pads of the semiconductor die to leads of the package substrate; and mold compound covering the magnetic concentrator, the semiconductor die, the electrical connections, a portion of the leads, and the die side surface of the die pad.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Rafael Jose Lizares Guevara, Dok Won Lee, Kashyap Mohan