Patents by Inventor Kasumasa Yanagisawa

Kasumasa Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory capable of simultaneously reading plural adjacent memory cells
    Patent number: 4965770
    Abstract: A semiconductor memory has a function which enables data to be simultaneously read out from four memory cells, that is, a first memory cell disposed at the intersection between a first data line and a first word line which correspond to address signals, respectively, a second memory cell disposed at the intersection between the first data line and a second word line to which is assigned a row address adjacent to the row address corresponding to the first word line, a third memory cell disposed at the intersection between the first word line and a second data line to which is assigned a column address adjacent to the column address corresponding to the first data line, and a fourth memory cell disposed at the intersection between the second data line and the second word line.
    Type: Grant
    Filed: September 25, 1987
    Date of Patent: October 23, 1990
    Assignee: Hitachi, Ltd.
    Inventor: Kasumasa Yanagisawa