Patents by Inventor Kasun Anupama Punchihewa

Kasun Anupama Punchihewa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10181522
    Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tuhin Guha Neogi, Scott D. Luning, David Pritchard, Kasun Anupama Punchihewa
  • Publication number: 20180240885
    Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Inventors: Tuhin Guha Neogi, Scott D. Luning, David Pritchard, Kasun Anupama Punchihewa
  • Patent number: 10056368
    Abstract: A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of the plurality of fins and in a second surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins. The doped region includes a first dopant having a first conductivity type and is contiguous between the adjacent fins. A cathode region is defined by an inner portion of each of the plurality of fins positioned below and contacting the first surface portion and a third portion of the semiconductor substrate positioned below and contacting the second surface portion. The cathode region is contiguous and the dopants in the cathode region and anode region have opposite conductivity types. A junction is defined between the anode region and the cathode region. A first contact interfaces with the anode region.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kasun Anupama Punchihewa, Jagar Singh
  • Publication number: 20180006019
    Abstract: A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of the plurality of fins and in a second surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins. The doped region includes a first dopant having a first conductivity type and is contiguous between the adjacent fins. A cathode region is defined by an inner portion of each of the plurality of fins positioned below and contacting the first surface portion and a third portion of the semiconductor substrate positioned below and contacting the second surface portion. The cathode region is contiguous and the dopants in the cathode region and anode region have opposite conductivity types. A junction is defined between the anode region and the cathode region. A first contact interfaces with the anode region.
    Type: Application
    Filed: August 25, 2017
    Publication date: January 4, 2018
    Inventors: Kasun Anupama Punchihewa, Jagar Singh
  • Publication number: 20170317071
    Abstract: A method incudes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a second width greater than the first width is formed in a second region of a semiconductor substrate. A doped region is formed in a surface portion of the second plurality of fins to define an anode region of a diode. A junction is defined between the doped region and a cathode region of the second plurality of fins. A first contact interfacing with the anode region is formed.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 2, 2017
    Inventors: Kasun Anupama Punchihewa, Jagar Singh
  • Patent number: 9793262
    Abstract: A method includes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a second width greater than the first width is formed in a second region of a semiconductor substrate. A doped region is formed in a surface portion of the second plurality of fins to define an anode region of a diode. A junction is defined between the doped region and a cathode region of the second plurality of fins. A first contact interfacing with the anode region is formed.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kasun Anupama Punchihewa, Jagar Singh