Patents by Inventor Katarina Paulsson

Katarina Paulsson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8271773
    Abstract: A configurable field device for automation technology with a partially dynamically reconfigurable logic chip FPGA, in which function modules are dynamically configured during runtime, and to a method for operating the configurable field device.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: September 18, 2012
    Assignee: Endress + Hauser GmbH + Co. KG
    Inventors: Udo Grittke, Armin Wernet, Roland Dieterle, Axel Humpert, Dietmar Frühauf, Romuald Girardey, Jürgen Becker, Michael Huebner, Katarina Paulsson
  • Publication number: 20110035576
    Abstract: A configurable field device for automation technology with a partially dynamically reconfigurable logic chip FPGA, in which function modules are dynamically configured during runtime, and to a method for operating the configurable field device.
    Type: Application
    Filed: September 10, 2007
    Publication date: February 10, 2011
    Applicant: Endress + Hauser GmbH + Co. KG
    Inventors: Udo Grittke, Armin Wernet, Roland Dieterle, Axel Humpert, Dietmar Fruhauf, Romuald Girardey, Jurgen Becker, Katarina Paulsson, Michael Hubner
  • Publication number: 20110025376
    Abstract: A system for the flexible configuration of function modules. The system includes the following components a plurality of logic cells in a fixedly wired FPGA/standard ASIC structure, wherein the logic cells are so configurable by means of configuration registers, that they execute basic logic functions; a switch matrix having a plurality of memory cells, via which different logical connections of the logic cells in defined complex connections are configurable by means of the configuration registers; and a control unit, which partially dynamically so configures the logic cells and the switch matrix via an internal bus and via the configuration registers by means of a configuration bit stream, that the fixedly wired FPGA/ASIC structure behaves functionally as a partially dynamically reconfigurable logic chip.
    Type: Application
    Filed: September 10, 2007
    Publication date: February 3, 2011
    Applicant: Endress + Hauser GmbH + Co. KG
    Inventors: Udo Grittke, Axel Humpert, Dietmar Fruhauf, Romuald Girardey, Jurgen Becker, Katarina Paulsson, Michael Hubner