Patents by Inventor Katarzyna KOWALIK
Katarzyna KOWALIK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230145562Abstract: A semiconductor device includes: a semiconductor body having a first surface, a second surface opposite to the first surface in a vertical direction, an active region, and a sensor region arranged adjacent to the active region in a horizontal direction; transistor cells at least partly integrated in the active region, each transistor cell including a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region; at least one sensor cell at least partly integrated in the sensor region, each sensor cell including a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region; and an intermediate region arranged between the active region and the sensor region, the intermediate region including a drift region and an undoped semiconductor region extending from the first surface into the drift region.Type: ApplicationFiled: October 31, 2022Publication date: May 11, 2023Inventors: Markus Wiesinger, Katarzyna Kowalik-Seidl, Armin Tilke, Armin Willmeroth
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Publication number: 20230119393Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces in a vertical direction, and transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes first and second source regions, first and second body regions, a drift region separated from the respective source region by the corresponding body region, a first gate electrode, and a control electrode. The drift region is arranged between the first and the second body region in a horizontal direction that is perpendicular to the vertical direction and extends from the first surface into the semiconductor body in the vertical direction. The first gate electrode is configured to provide a control signal for switching the transistor cell. The control electrode is configured to provide a control signal for controlling a JFET formed by the first body region, the drift region, and the second body region.Type: ApplicationFiled: October 14, 2022Publication date: April 20, 2023Inventors: Katarzyna Kowalik-Seidl, Armin Tilke, Markus Wiesinger
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Publication number: 20220384567Abstract: A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.Type: ApplicationFiled: May 17, 2022Publication date: December 1, 2022Inventors: Rolf Weis, Franz Hirler, Katarzyna Kowalik-Seidl, Marco Mueller, Anthony Sanders
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Patent number: 10943987Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm?3.Type: GrantFiled: June 25, 2019Date of Patent: March 9, 2021Assignee: Infineon Technologies Austria AGInventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
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Patent number: 10692970Abstract: A semiconductor device include a semiconductor body with a drain region of a first conductivity type, a drift region of the first conductivity type and having a doping concentration lower than a doping concentration of the drain region, a buffer region of the first conductivity type arranged between the drift region and the drain region, a source region of the first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region and forming a first pn-junction with the source region and a second pn-junction with the drift region, and a charge compensation region of the second conductivity type extending from the body region towards the buffer region. A source metallization is in ohmic contact with the source region. A drain metallization is ohmic contact with the drain region.Type: GrantFiled: November 14, 2018Date of Patent: June 23, 2020Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Katarzyna Kowalik-Seidl, Ayad Abdul-Hak, Olaf Fiedler, Richard Hensch, Markus Schmitt, Daniel Kai Simon
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Publication number: 20200044064Abstract: A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.Type: ApplicationFiled: October 15, 2019Publication date: February 6, 2020Inventors: Joachim Weyers, Katarzyna Kowalik-Seidl, Andreas Schloegl, Enrique Vecino Vazquez
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Patent number: 10483383Abstract: A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.Type: GrantFiled: March 14, 2018Date of Patent: November 19, 2019Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Joachim Weyers, Katarzyna Kowalik-Seidl, Andreas Schloegl, Enrique Vecino Vazquez
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Publication number: 20190319110Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm?3.Type: ApplicationFiled: June 25, 2019Publication date: October 17, 2019Inventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
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Patent number: 10374056Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.Type: GrantFiled: October 28, 2016Date of Patent: August 6, 2019Assignee: Infineon Technologies Austria AGInventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
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Patent number: 10308935Abstract: The present application relates to a method for the targeted formation of heterochromatin and/or induction of epigenetic gene silencing in a cell using a small RNA, said method comprising the step of inhibiting the Paf1 complex in said cell and the step of contacting said cell with a small RNA targeted to a region of the genome of the cell, said region being the region where heterochromatin formation and/or induction of epigenetic gene silencing should be induced.Type: GrantFiled: June 22, 2015Date of Patent: June 4, 2019Assignee: FRIEDRICH MIESCHER INSTITUTE FOR BIOMEDICAL RESEARCHInventors: Marc Buehler, Katarzyna Kowalik, Yukiko Shimada
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Publication number: 20190148484Abstract: A semiconductor device include a semiconductor body with a drain region of a first conductivity type, a drift region of the first conductivity type and having a doping concentration lower than a doping concentration of the drain region, a buffer region of the first conductivity type arranged between the drift region and the drain region, a source region of the first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region and forming a first pn-junction with the source region and a second pn-junction with the drift region, and a charge compensation region of the second conductivity type extending from the body region towards the buffer region. A source metallization is in ohmic contact with the source region. A drain metallization is ohmic contact with the drain region.Type: ApplicationFiled: November 14, 2018Publication date: May 16, 2019Inventors: Katarzyna Kowalik-Seidl, Ayad Abdul-Hak, Olaf Fiedler, Richard Hensch, Markus Schmitt, Daniel Kai Simon
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Publication number: 20180269296Abstract: A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.Type: ApplicationFiled: March 14, 2018Publication date: September 20, 2018Inventors: Joachim Weyers, Katarzyna Kowalik-Seidl, Andreas Schloegl, Enrique Vecino Vazquez
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Patent number: 9929727Abstract: In accordance with an embodiment, a method of operating a semiconductor switch coupled to an inductor includes turning on the semiconductor switch by applying a turn-on voltage to between a gate of the semiconductor switch and a low current terminal connected to a reference node of the semiconductor switch, the low current terminal separate from a high current reference terminal connected to the reference node of the semiconductor switch, and the semiconductor switch comprises a first input capacitance to transconductance ratio. The method further includes turning off the semiconductor switch by applying a turn-off voltage to the gate of the semiconductor switch, wherein a ratio of a total capacitance at an output node of the semiconductor switch to a gate-drain capacitance is greater than a first ratio per watt of power being handled by a load coupled to the semiconductor switch.Type: GrantFiled: June 23, 2016Date of Patent: March 27, 2018Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Enrique Vecino Vazquez, Katarzyna Kowalik Seidl
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Publication number: 20170242949Abstract: According to various embodiments, a transistor model for a computer based simulation of a field effect transistor may include: a first electrical network coupled between a drain node, a source node and a gate node, wherein the first electrical network is configured to represent an electrical characteristic of the field effect transistor in a forward operation; a second electrical network coupled parallel to the first electrical network and between the source node and the drain node, wherein the second electrical network is configured to represent an electrical characteristic of the field effect transistor in at least one of a commutation operation and a reverse operation; wherein the second electrical network includes: a controlled first source representing a parasitic junction of the field effect transistor; at least one controlled second source representing a charge injection dependent parasitic impedance of the field effect transistor; wherein the controlled first source and the at least one controlled secType: ApplicationFiled: February 14, 2017Publication date: August 24, 2017Inventors: Patrick Schindler, Katarzyna Kowalik-Seidl, Franz Hirler
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Publication number: 20170152514Abstract: The present application relates to a method for the targeted formation of heterochromatin and/or induction of epigenetic gene silencing in a cell using a small RNA, said method comprising the step of inhibiting the Paf1 complex in said cell and the step of contacting said cell with a small RNA targeted to a region of the genome of the cell, said region being the region where heterochromatin formation and/or induction of epigenetic gene silencing should be induced.Type: ApplicationFiled: June 22, 2015Publication date: June 1, 2017Inventors: Marc BUEHLER, Katarzyna KOWALIK, Yukiko SHIMADA
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Publication number: 20170125580Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.Type: ApplicationFiled: October 28, 2016Publication date: May 4, 2017Inventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
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Publication number: 20170019096Abstract: In accordance with an embodiment, a method of operating a semiconductor switch coupled to an inductor includes turning on the semiconductor switch by applying a turn-on voltage to between a gate of the semiconductor switch and a low current terminal connected to a reference node of the semiconductor switch, the low current terminal separate from a high current reference terminal connected to the reference node of the semiconductor switch, and the semiconductor switch comprises a first input capacitance to transconductance ratio. The method further includes turning off the semiconductor switch by applying a turn-off voltage to the gate of the semiconductor switch, wherein a ratio of a total capacitance at an output node of the semiconductor switch to a gate-drain capacitance is greater than a first ratio per watt of power being handled by a load coupled to the semiconductor switch.Type: ApplicationFiled: June 23, 2016Publication date: January 19, 2017Inventors: Enrique Vecino Vazquez, Katarzyna Kowalik Seidl
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Patent number: 9219149Abstract: A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure.Type: GrantFiled: July 5, 2013Date of Patent: December 22, 2015Assignee: Infineon Technologies Dresden GmbHInventors: Anton Mauder, Katarzyna Kowalik-Seidl, Rolf Weis, Uwe Wahl
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Publication number: 20150008517Abstract: A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure.Type: ApplicationFiled: July 5, 2013Publication date: January 8, 2015Inventors: Anton Mauder, Katarzyna Kowalik-Seidl, Rolf Weis, Uwe Wahl