Abstract: A reconfigurable processing device comprises one or more reconfigurable processing units. At least one processing unit utilizes a computational unit having a preprocessing module for receiving n input signals, and s1 selection signals, and providing k output signals wherein k<n+s1. The computational unit further comprises an m-output look-up table being addressed by the k output signals of the preprocessing module and an output multiplexer for selecting one of the m output signals of the look-up table under control of s2 further selection signals.

Abstract: A method is provided which creates an architecture of a reconfigurable logic core. The architecture can be deployed for various purposes and its implementation is costefficient in terms of area, performance and power. The invention relies on the perception that a template can be used to describe such an architecture. The architecture can then easily be created as an instance of the template. The template is a model which defines logic components, routing components and interface components of a reconfigurable logic core. For example, logic components may be logic elements, processing elements, logic blocks, logic tiles and arrays in a hierarchical order. Routing components may comprise routing channels comprising routing tracks which provide interconnection means between the logic components. Interface components may be input and output ports. The model is configured by a number of parameters; the value of these parameters is in accordance with an application domain.

Abstract: An integrated circuit (300) has a regular grid formed by substantially identical building blocks (100a-i). To avoid possible routing conflicts around the edges of the integrated circuit (300), which can be introduced by the use of a single type of an asymmetric building block, the integrated circuit (300) is extended with routing cells (200) that provide routing at the edges of the grid that are uncovered by the routing networks of the building blocks (100a-i). The routing cells (200) and the switch cell (250) are combined with a first routing structure (330) and a second routing structure (340) to form a routing network (280) surrounding the grid of the integrated circuit (300). Consequently, an integrated circuit (300) is presented that comprises only a single type of building block (100a-i) but still has a fully symmetric routing architecture.

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. An output circuit passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units have look-up tables which share the same configuration bits. The programmable logic units can also have multiplexers for passing one of the received input signals when configured to operate in a multiplexing mode of operation.

Abstract: A reconfigurable logic device according to the invention comprises a lookup table (LUT) (11.1) with an input (in 1) for receiving an input signal and an output (out) for providing a binary output signal. The reconfigurable logic device is characterized by, a control input (ctrl) for receiving a control bit, a controllable inverting gate (11.2) for providing the address signal to the LUT (11.1) in response to the control bit and the input signal, and by a controllable inverting gate (11.3) for providing a modified output signal in response to the output signal of the LUT and the control bit. The reconfigurable logic device according to the invention can operate at a high speed, and at the same time have a relatively modest configuration memory.

Abstract: A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, . . . ) for storing settings of the data flow controlling elements (10) and an address decoder (40) for converting an address into selection signals for the memory cells (31a, . . . ). The reconfigurable processing unit of the invention is characterized in that the address decoder (40) is shared between the configuration memory unit (30) and a further memory unit (20), or between two configuration memory units (30, 30?). This provides for a reduction in memory area of the reconfigurable processing unit (1).

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain.

Abstract: A reconfigurable electronic device (100), e.g., a field programmable gate array (FPGA) or another type of complex programmable logic device (CPLD), has a first data storage device (120) and a second storage device (220) that are interconnected in a dual port memory mode of the reconfigurable electronic device (100). In this mode, the first data storage device (120) is accessible by a first decoder (140) both in a read as well as in a write mode, and the second data storage device (120) is accessible by a second decoder (140) in a read mode, thus providing an efficient dual port memory implementation. In a preferred embodiment, the first data storage device (120) is coupled to the second data storage device (220) via a configurable data copy circuit (160) that is responsive to a configuration signal provided via a configuration signal input (170), thus allowing for a very area efficient implementation of a dual port memory for reconfigurable electronic device (100).

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. An output circuit passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units have look-up tables which share the same configuration bits. The programmable logic units can also have multiplexers for passing one of the received input signals when configured to operate in a multiplexing mode of operation.

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain.

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain.

Abstract: The present invention relates to a method and apparatus for decoding a sequence of at least two instructions of a data processing program into a sequence of code words used to control a data path, wherein an invariant code word portion which does not change in said sequence of code words is separately generated and used to configure a part of the data path to be fixed during the sequence of code words. Thereby, the necessary micro code memory size can be reduced and power consumption can be decreased.

Abstract: A reconfigurable electronic device (100), e.g., a field programmable gate array (FPGA) or another type of complex programmable logic device (CPLD), has a first data storage device (120) and a second storage device (220) that are interconnected in a dual port memory mode of the reconfigurable electronic device (100). In this mode, the first data storage device (120) is accessible by a first decoder (140) both in a read as well as in a write mode, and the second data storage device (120) is accessible by a second decoder (140) in a read mode, thus providing an efficient dual port memory implementation. In a preferred embodiment, the first data storage device (120) is coupled to the second data storage device (220) via a configurable data copy circuit (160) that is responsive to a configuration signal provided via a configuration signal input (170), thus allowing for a very area efficient implementation of a dual port memory for reconfigurable electronic device (100).

Abstract: An integrated circuit (300) has a regular grid formed by substantially identical building blocks (100a-i). To avoid possible routing conflicts around the edges of the integrated circuit (300), which can be introduced by the use of a single type of an asymmetric building block, the integrated circuit (300) is extended with routing cells (200) that provide routing at the edges of the grid that are uncovered by the routing networks of the building blocks (100a-i). The routing cells (200) and the switch cell (250) are combined with a first routing structure (330) and a second routing structure (340) to form a routing network (280) surrounding the grid of the integrated circuit (300). Consequently, an integrated circuit (300) is presented that comprises only a single type of building block (100a-i) but still has a fully symmetric routing architecture.

Abstract: An electronic device (100) has a data storage device (120) for storing N data elements, the data storage device (120) comprising a first collection (122) of data storage elements (130). The first collection (122) of data storage elements (130) is accessible through an address decoder (140). In a shift register mode of the data storage device (120), the address decoder (140) is responsive to an address generator (160) comprising a modulo-N counter. Rather than having to shift data elements from one data storage element (130) to another, the address generator (160) generates a pointer to the data storage element (130) that contains the data element that is to be shifted out of the shift register. This has the advantage that the output of a predecessor data storage element (130) in a shift register need not be interconnected to the input of its successor. In addition, the amount of data traffic required during a shift is drastically reduced.

Abstract: A reconfigurable processing device comprising one or more reconfigurable processing units is disclosed. At least a processing unit includes a computational unit having a preprocessing module for receiving n input signals, and s1 selection signals, and providing k output signals wherein k<n+s1. The computational unit further comprises a m-output look-up table being addressed by the k output signals of the preprocessing module and an output multiplexer for selecting one of the m output signals of the look-up table under control of s2 further selection signals. This allows for the implementation of relatively large multiplexers also in architectures using multi-bit output LUTs. In addition a reconfigurable processing unit is described having an input multiplexer for selecting input signal from a communication network, which input multiplexer is configurable statically or dynamically.

Abstract: A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, . . . ) for storing settings of the data flow controlling elements (10) and an addres decoder (40) for converting an address into selection signals for the memory cells (31a, . . . ). The reconfigurable processing unit of the invention is characterized in that the address decoder (40) is shared between the configuration memory unit (30) and a further memory unit (20), or between two configuration memory units (30, 30?). This provides for a reduction in memory area of the reconfigurable processing unit (1).

Abstract: A reconfigurable logic device according to the invention comprises a lookup table (LUT) (11.1) with an input (in1) for receiving an input signal and an output (out) for providing a binary output signal. The reconfigurable logic device is characterized by, a control input (ctrl) for receiving a control signal, a controllable inverting gate (11.2) for providing the address signal to the LUT (11.1) in response to the control signal and the input signal, and by a controllable inverting gate (11.3) for providing a modified output signal in response to the output signal of the LUT and the control signal.

Abstract: An integrated circuit has a matrix of programmable cells. Programmable switches connect pairs of neighboring cells. Each cell contains a local conductor connecting a pair of the switches on opposite sides of the cell. Each switch connects the local conductors of the neighboring cells. At least one of the cells have a computation logic circuit having either an input connected to the local conductor of the at least one of the cells. The computation logic circuit has programmably individually activatable outputs connected to the local conductors of neighbor cells of the at least one of the cells or an output connected to the local conductor of the at least one of the cells and programmably individually activatable inputs connected to the local conductors of neighbor cells of the at least one of the cells.