Abstract: A layered structure is described incorporating a noble metal silicide, a noble metal and an oxygen-rich barrier layer between the noble metal silicide and noble metal. A silicon-contributing substrate may also be present in addition to or without the noble metal silicide. The invention overcomes a problem in fabricating capacitors containing high-epsilon dielectric materials or ferroelectric memory elements containing ferroelectric material, namely that silicon diffuses through the electrode in one direction and oxygen diffuses through the electrode in the other direction during the high temperature (400-700.degree. C.) deposition and processing of the dielectric.

Abstract: A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.

Abstract: A structured dielectric layer and fabrication process for separating wiring levels and wires within a level on a semiconductor chip is described incorporating a lower dielectric layer having narrow air gaps to form dielectric pillars or lines and an upper dielectric layer formed over the pillars or fine lines wherein the air gaps function to substantially reduce the effective dielectric constant of the structured layer. The invention overcomes the problem of solid dielectric layers which would have the higher dielectric constant of the solid material used.

Abstract: This invention is directed to a semiconductor memory device including a storage element having a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.

Abstract: Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.

Abstract: Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

Abstract: A capacitor structure with a generally L-shaped non-conductor having a horizontal portion and a vertical portion, the vertical portion defining a first opening formed therein; a generally U-shaped conductor formed within the first opening; and a generally L-shaped conductor formed exterior to the generally L-shaped non-conductor.

Abstract: A capacitor structure is provided, with a first conductor on top of a substrate having at least one layer of dielectric material thereon; a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein; a second conductor, in electrical contact with the first conductor, formed on the sidewalls of the first opening; a non-conductive sidewall spacer formed in the first opening and contacting the second conductor, the non-conductive sidewall spacer having a second opening formed therein; and a third conductor formed in the second opening.