Patents by Inventor Katherine Wagenhoffer

Katherine Wagenhoffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7732914
    Abstract: A process for fabricating a cavity-type integrated circuit includes supporting a leadframe strip in a mold. The leadframe strip includes a die attach pad and a row of contact pads circumscribing the die attach pad. A package body is molded in the mold such that opposing surfaces of the die attach pad and of the contact pads are exposed. A semiconductor die is mounted to the die attach pad. Various ones of the contact pads are wire bonded to the semiconductor die and a lid is mounted on the package body to thereby enclose the semiconductor die and the wire bonds in a cavity of the integrated circuit package.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: June 8, 2010
    Inventors: Neil McLellan, Katherine Wagenhoffer, Geraldine Tsui Yee Lin, Mohan Kirloskar
  • Patent number: 7348663
    Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: March 25, 2008
    Assignee: ASAT Ltd.
    Inventors: Mohan Kirloskar, Katherine Wagenhoffer, Leo M. Higgins, III
  • Patent number: 7344920
    Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: March 18, 2008
    Assignee: ASAT Ltd.
    Inventors: Mohan Kirloskar, Katherine Wagenhoffer, Leo M. Higgins, III