Patents by Inventor Kathleen C. Yu
Kathleen C. Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7904869Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.Type: GrantFiled: December 18, 2007Date of Patent: March 8, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Kathleen C. Yu, Scott D. Hector, Robert L. Maziasz, Claudia A. Stanley, James E. Vasck
-
Publication number: 20090158229Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Inventors: Kathleen C. Yu, Scott D. Hector, Robert L. Maziasz, Claudia A. Stanley, James E. Vasck
-
Patent number: 7176574Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.Type: GrantFiled: September 22, 2004Date of Patent: February 13, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
-
Patent number: 7122421Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.Type: GrantFiled: April 4, 2005Date of Patent: October 17, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Hector Sanchez, Michael A. Mendicino, Byoung W. Min, Kathleen C. Yu
-
Patent number: 7030001Abstract: One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.Type: GrantFiled: April 19, 2004Date of Patent: April 18, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Olubunmi O. Adetutu, Lynne M. Michaelson, Kathleen C. Yu, Robert E. Jones, Jr.
-
Patent number: 6921961Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.Type: GrantFiled: September 22, 2004Date of Patent: July 26, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Hector Sanchez, Michael A. Mendicino, Byoung W. Min, Kathleen C. Yu
-
Patent number: 6838354Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.Type: GrantFiled: December 20, 2002Date of Patent: January 4, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
-
Patent number: 6838332Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.Type: GrantFiled: August 15, 2003Date of Patent: January 4, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Hector Sanchez, Michael A. Mendicino, Byoung W. Min, Kathleen C. Yu
-
Patent number: 6815820Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.Type: GrantFiled: May 9, 2002Date of Patent: November 9, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
-
Patent number: 6764919Abstract: Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.Type: GrantFiled: December 20, 2002Date of Patent: July 20, 2004Assignee: Motorola, Inc.Inventors: Kathleen C. Yu, Edward O. Travis, Bradley P. Smith
-
Publication number: 20040119134Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
-
Publication number: 20040121577Abstract: Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Kathleen C. Yu, Edward O. Travis, Bradley P. Smith
-
Publication number: 20030209779Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.Type: ApplicationFiled: May 9, 2002Publication date: November 13, 2003Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
-
Patent number: 6313024Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.Type: GrantFiled: September 10, 1999Date of Patent: November 6, 2001Assignee: Motorola, Inc.Inventors: Nigel G. Cave, Kathleen C. Yu, Janos Farkas
-
Patent number: 6037668Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.Type: GrantFiled: November 13, 1998Date of Patent: March 14, 2000Assignee: Motorola, Inc.Inventors: Nigel G. Cave, Kathleen C. Yu, Janos Farkas