Abstract: A method for controlling an amplitude of an incoming light is provided. The method includes attenuating a portion of the incoming light within a first band having a tunable peak attenuation wavelength using a tunable filter; passing a portion of the incoming light from the tunable filter within a second band using a fixed filter; and controlling the amplitude of the incoming light by tuning the peak attenuation wavelength of the tunable filter.

Abstract: A unit cell of a narrow band filter is provided. The unit cell includes a matrix body having a first permittivity and an inclusion body having a second permittivity and disposed in the matrix body. The matrix body and the inclusion body are configured to reflect electromagnetic radiation incident on electromagnetic radiation facing surfaces of the matrix body and the inclusion body. A bandwidth of the reflected electromagnetic radiation is based on a difference between the first permittivity and a third permittivity, which is an average permittivity between the first permittivity and the second permittivity based on volumes of the inclusion body and a portion of the matrix body. The inclusion body is configured such that the second permittivity is adjustable to adjust the third permittivity, thereby adjusting the difference between the first permittivity and the third permittivity. A narrow band filter and a method are also disclosed.

Abstract: A plurality of processors each includes a central processor unit for processing programs at predetermined synchronization priority levels and a cache memory. A memory shared by all of the processors includes an synchronization level table which identifies a processor operating at each synchronization priority level. A common bus interconnects the processors and the memory. When a processor is to execute a program, it adjusts its synchronization priority level to a predetermined synchronization priority level by accessing the synchronization level table over the common bus to determine whether the level is accessible and, if so, places an entry in the table to indicate that the synchronization priority level is occupied. If the synchronization priority level is not accessible, the processor continually monitors the entry in the table over the common bus to determine when it is accessible by monitoring its cache, which contains a copy of the table entry associated with the synchronization priority level.