Abstract: The invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction. The apparatus and method employ: a low precision floating point adder/subtractor, a priority encoder that determines the position of the most significant non-zero bit to generate the normalization amount and preround logic which pre-shifts a rounding bit in the opposite direction of normalization. The method and apparatus operate in parallel with a full precision floating point adder to eliminate the need for a full-precision floating point normalization calculation and rounding computation in most circumstances. The normalization amount for successful low-precision floating-point addition/subtraction is calculated by the time the full-precision floating-point addition/subtraction stage occurs.