Abstract: In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell.

Abstract: In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a photoresist over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the photoresist having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the photoresist, the sidewall film having a vertical portion adjacent the sidewall of the photoresist and a horizontal portion in areas not adjacent the sidewall of the photoresist; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the photoresist exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewa

Abstract: In the manufacture of sub-0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

Abstract: In one embodiment, the present invention relates to a method of forming a thin photoresist layer having a low defect density, involving the steps of depositing a photoresist layer having a thickness from greater than about 0.5 &mgr;m to about 2 &mgr;m on a semiconductor substrate; and removing at least a portion of the photoresist layer to provide the thin photoresist layer having the low defect density and a thickness from about 0.1 &mgr;m to about 0.5 &mgr;m. In another embodiment, the present invention relates to a method of reducing pinhole defects in a thin photoresist layer having a thickness below about 0.5 &mgr;m comprising a photoresist material, involving the steps of depositing a layer of the photoresist material having a thickness greater than about 0.5 &mgr;m; and etching at least a portion of the photoresist material to provide the thin photoresist layer having the thickness below about 0.

Abstract: A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions.

Abstract: In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a sidewall template over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the sidewall template having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the sidewall template, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template and a horizontal portion in areas not adjacent the sidewall of the sidewall template; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the sidewall template exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlyin

Abstract: The present invention relates to wafer alignment. A reticle is employed which includes, a design and first and second alignment marks. The second alignment mark is symmetric to the first alignment mark such that a reticle center point is a midpoint of the first and second alignment marks. The first alignment mark is printed on a surface layer of the wafer. The second alignment mark is printed on the surface layer at an offset from the first alignment mark. A virtual alignment mark is determined, the virtual alignment mark being a midpoint of the printed first and second alignment marks. The virtual alignment mark is employed to facilitate aligning the wafer. The symmetric relationship between the first and second alignment mark results in the negation of print errors of the marks due to reticle rotation and/or lens magnification with respect to the virtual alignment mark. The employment of the virtual alignment mark in wafer alignment substantially facilitates mitigation of overlay error.

Abstract: In the manufacture of sub 0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. The method including forming a first polysilicon (poly I) layer on an oxide coated substrate and masking the poly I layer to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator such that the insulator electrically isolates the poly I layer (e.g., floating gate) of the first memory cell from the poly I layer (e.g., floating gate) of the second memory cell.

Abstract: In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a mask over a first portion of the conductive film wherein a second portion of the conductive film is exposed; partially etching the second portion of the conductive film thereby forming a sidewall in the conductive film; removing the mask; depositing a sidewall film over the conductive film, the sidewall film having a vertical portion adjacent the sidewall of the conductive film and a horizontal portion in areas not adjacent the sidewall of the conductive film; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; and etching the third portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.

Abstract: A method of repairing defects in a photomask used in the formation of a semiconductor wafer includes the use of a scanning tunneling microscope. The scanning tunneling microscope includes a very sharp tip having a diameter on the order of 100 Å or less. In order to remove excess material from a mask layer in the photomask, the tip is placed into contact with those regions having such excess material and the tip is used to scrape the excess material away. In order to add material to voids in a mask layer of the photomask, the tip is placed in proximity to those areas in need of the excess material and caused to deposit such material upon, for example, application of a bias voltage to the tip.

Abstract: A reflective element for extreme ultraviolet semiconductor lithography systems substantially minimizes the phase transitions of reflected extreme ultraviolet light by a reflective multilayer coating on an extremely planar surface which is parallel to a family of (111) crystallographic planes of a single crystal silicon wafer. The extremely planar surface is made by using three of the families of (111) crystallographic planes of the single crystal silicon as etch barriers for anisotropic etchants.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell.

Abstract: A method for fabricating a vertical parallel plate capacitor is provided. In the method, a sacrificial layer is formed on at least a portion of a surface. A dielectric layer is conformally formed on the sacrificial layer and an exposed portion of the surface. The dielectric layer is etched so as to leave substantially only a fence of dielectric material along a sidewall of the sacrificial layer. The sacrificial layer is removed, and a conductive layer is deposited on the fence and surface. The conductive layer is etched and planarized so as to form a first capacitor plate along one side of the fence, and a second capacitor plate along the other side of the fence, the first and second capacitor plates being substantially parallel to each other, and transverse sections of the capacitor plates including elongated portions substantially normal to the surface.

Abstract: A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O.sub.2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.

Abstract: A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.

Abstract: A reflective element for extreme ultraviolet semiconductor lithography systems substantially minimizes the phase transitions of reflected extreme ultraviolet light by a reflective multilayer coating on an extremely planar surface which is parallel to a family of (111) crystallographic planes of a single crystal silicon wafer. The extremely planar surface is made by using three of the families of (111) crystallographic planes of the single crystal silicon as etch barriers for anisotropic etchants.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. The method including forming a first polysilicon (poly I) layer on an oxide coated substrate and masking the poly I layer to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator such that the insulator electrically isolates the poly I layer (e.g., floating gate) of the first memory cell from the poly I layer (e.g., floating gate) of the second memory cell.