Abstract: A data merge unit is provided for providing an interleaved data stream, the data stream including data frames received on two or more input channels, wherein data frames from each of the two or more input channels are arranged in time-slots of the interleaved data stream. The data merge unit comprises an input unit to receive data frames from two or more input channels, a frame merge buffer arranged to receive data frames from the two or more input channels via the input unit and store said data frames; and, an output generator to generate the interleaved data stream, the output generator being configured to select complete data frames from the frame merge buffer and arrange said complete data frames in the interleaved data stream.

Abstract: A direct memory access controller includes a source memory controller for controlling a source memory, a destination bus controller for controlling the transfer of data to a destination memory, a first-in-first-out memory buffer for receiving data from the source memory, and a filter connected upstream of the first-in-first-out memory buffer for comparing the source memory data to a filter criterion and passing to the first-in-first-out memory buffer only that data which matches the filter criterion.

Abstract: A method and system for partial reassembly of data frames reconstructed from data cells received from a network data stream includes partially reassembling the header cells and the last cell of each frame and passing the remainder of data frame cells to a capture buffer in an unassembled state. Since the partially reassembled data frames include only a subset of each frame, they can be processed at the full line-rate of the network data stream without causing an overflow. The cells in the partially reassembled frames are only those cells required for functions that must be performed at the full line rate.

Abstract: In a method for enabling filtering of data packets passing along a data link (10), each data packet to be filtered includes connection data relating to the source of the data packet and the destination of the data packet. For at least some of the data packets passing along a data link, the connection data of the data packets is compared in a hardware logic device (24) with connection data stored in the hardware logic device (24). A positive evaluation result is generated for any packet for which the connection data of the data packet matches any of the connection data stored in the hardware logic device (24), whereby the data packet can be filtered. For a packet whose connection data does not match connection data that has been previously stored in the hardware logic device (24), connection data for the packet is preferably added to the connection data stored in the hardware logic device (24). The hardware logic device (24) may be a content addressable memory (CAM).

Abstract: Video subsystem power savings are achieved by shutting off power to unused subcircuits during blanking. Digital circuitry within the video subsystem not used during blanking is shut-down by turning off the clock thereto. Analog circuitry within a digital to analog converter is shut-down by turning off the constant current reference thereto. A functional unit containing digital circuitry within a serializer palette digital to analog converter (SPDAC) is shut-down by turning off the clock thereto during system operation in a mode where the functional unit is not utilized. A computer system having a monochrome display saves power by shutting off DAC digital circuitry clocks and DAC analog circuitry constant current references of all DACs but one. A portable computer with a liquid crystal display (LCD), a SPDAC for driving an external display and a LCD controller, saves power by shutting down video subsystem functional units and analog DAC circuitry not used for driving the LCD.