Patents by Inventor Kathryn Guarini
Kathryn Guarini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8901741Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.Type: GrantFiled: June 23, 2012Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
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Patent number: 8358011Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.Type: GrantFiled: September 7, 2007Date of Patent: January 22, 2013Assignee: International Business Machines CorporationInventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
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Publication number: 20130009315Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.Type: ApplicationFiled: September 7, 2007Publication date: January 10, 2013Inventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
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Publication number: 20120261823Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.Type: ApplicationFiled: June 23, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
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Publication number: 20080096330Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.Type: ApplicationFiled: December 18, 2007Publication date: April 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Doris, Kathryn Guarini, Meikei Ieong, Shreesh Narasimha, Kern Rim, Jeffrey Sleight, Min Yang
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Publication number: 20080042140Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.Type: ApplicationFiled: August 30, 2007Publication date: February 21, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPERATIONInventors: Syed Alam, Ibrahim Elfadel, Kathryn Guarini, Meikei Ieong, Prabhakar Kudva, David Kung, Mark Lavin, Arifur Rahman
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Publication number: 20070287224Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.Type: ApplicationFiled: April 19, 2007Publication date: December 13, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPERATIONInventors: Syed Alam, Ibrahim Elfadel, Kathryn Guarini, Meikei Ieong, Prabhakar Kudva, David Kung, Mark Lavin, Arifur Rahman
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Publication number: 20070218621Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: ApplicationFiled: April 10, 2007Publication date: September 20, 2007Applicant: International Business Machines CorporationInventors: Huiling Shang, Meikei Leong, Jack Chu, Kathryn Guarini
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Patent number: 7268432Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.Type: GrantFiled: October 10, 2003Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
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Publication number: 20070138556Abstract: A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.Type: ApplicationFiled: February 16, 2007Publication date: June 21, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Omer Dokumaci, Bruce Doris, Kathryn Guarini, Suryanarayan Hegde, Meikei Ieong, Erin Jones
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Publication number: 20060214301Abstract: A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.Type: ApplicationFiled: May 9, 2006Publication date: September 28, 2006Inventors: David Frank, Kathryn Guarini, Christopher Murray, Xinlin Wang, Hon-Sum Wong
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Publication number: 20060194414Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.Type: ApplicationFiled: April 26, 2006Publication date: August 31, 2006Applicant: International Business Machines CorporationInventors: Kevin Chan, Kathryn Guarini, Erin Jones, Antonio Saavedra, Leathen Shi, Dinkar Singh
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Publication number: 20060163646Abstract: A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.Type: ApplicationFiled: March 13, 2006Publication date: July 27, 2006Applicant: International Business Machines CorporationInventors: Charles Black, Kathryn Guarini
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Publication number: 20060033110Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.Type: ApplicationFiled: August 16, 2004Publication date: February 16, 2006Inventors: Syed Alam, Ibrahim Elfadel, Kathryn Guarini, Meikei Ieong, Prabhakar Kudva, David Kung, Mark Lavin, Arifur Rahman
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Publication number: 20050285097Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: ApplicationFiled: June 24, 2004Publication date: December 29, 2005Inventors: Huiling Shang, Meikei Ieong, Jack Chu, Kathryn Guarini
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Publication number: 20050285159Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the <110> and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas.Type: ApplicationFiled: June 24, 2004Publication date: December 29, 2005Applicant: International Business Machines CorporationInventors: Kevin Chan, Kathryn Guarini, Meikel Ieong, Kern Rim, Min Yang
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Publication number: 20050236687Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.Type: ApplicationFiled: April 22, 2004Publication date: October 27, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Chan, Bruce Doris, Kathryn Guarini, Meikei Ieong, Shreesh Narasimha, Alexander Reznicek, Kern Rim, Devendra Sadana, Leathen Shi, Jeffrey Sleight, Min Yang
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Publication number: 20050079719Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.Type: ApplicationFiled: October 10, 2003Publication date: April 14, 2005Inventors: Matthew Colburn, Satya Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
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Publication number: 20050070077Abstract: The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.Type: ApplicationFiled: October 18, 2004Publication date: March 31, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kathryn Guarini, Meikei Ieong, Leathen Shi, Min Yang
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Publication number: 20050067620Abstract: Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias.Type: ApplicationFiled: August 9, 2004Publication date: March 31, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Kathryn Guarini, Meikei Ieong