Abstract: Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is coupled between the coprocessor and a processor, where the controller is configured with a state machine to track the instruction through pipeline stages of the processor.

Abstract: Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a subset of coprocessor instructions, excluding user-selected instructions not instantiated. The processor is coupled to the coprocessor via a controller. The coprocessor instruction is sent from the processor to the controller, which queries control logic to determine whether the coprocessor is configured to execute the coprocessor instruction. If a control bit is set to disable an instruction or group of instructions, the coprocessor instruction is not executable by the coprocessor.

Abstract: A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the first frequency is a frequency of operation of the processor. The controller is coupled to the coprocessor to provide a coprocessor interface for operating at a second frequency, where the second frequency is a frequency of operation of the coprocessor which is slower than or equal to the first frequency. The controller is configured to operate at both the first frequency and the second frequency providing in part handshaking between the processor and the coprocessor such that the processor does not have to be slowed down to the second frequency for operation with the coprocessor.

Abstract: Method and apparatus for a decoder interface for a processor and a coprocessor is described. An input instruction register stores an input instruction from the processor. Configuration instruction registers store instructions. Comparison/pointer logic coupled to the input instruction register and the configuration instruction registers is configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, and configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having a instruction of the instructions matching the input instruction, where the pointer has fewer bits than the input instruction.

Abstract: Method and apparatus for non-lock-step operation between a processor and a controller is described. An instruction is provided from the processor to the controller. A busy signal is provided from the controller to the processor to indicate that the controller is not ready to execute the instruction. Initiation of execution of the instruction by the controller is done while continuing to indicate to the processor that the controller is not ready to execute the instruction.

Abstract: An interface for accessing a bank of registers is described. A controller is coupled to receive address information, read information and write information. The device control register interface includes: a data bus for receiving data, pointer information and operation delineation information; a decoder coupled to receive the read information, the write information, the pointer information and the operation delineation information, where the decoder is configured to provide activation signaling responsive to information received; and the bank of registers coupled to the decoder to receive the activation signaling and coupled to the data bus for receiving the data, where the address information is for the bank or registers and where a single address is used for accessing all registers in the bank of registers.