Patents by Inventor Kathryn Turner Schoenenberg

Kathryn Turner Schoenenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Spacers for FinFETs (Field Effect Transistors)
    Patent number: 7646070
    Abstract: A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: January 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak, Kathryn Turner Schoenenberg
  • SPACERS FOR FINFETS (FIELD EFFECT TRANSISTORS)
    Publication number: 20080217694
    Abstract: A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.
    Type: Application
    Filed: May 21, 2008
    Publication date: September 11, 2008
    Inventors: Brent Alan Anderson, Edward Joseph Nowak, Kathryn Turner Schoenenberg