Patents by Inventor Kathy Wei Yan

Kathy Wei Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395770
    Abstract: An Integrated Circuit (IC) structure includes a bottom level IC die and one or more top level IC dies. A first side of the one or more top level IC dies is bonded to the bottom IC die. A supporting substrate is coupled to a second side of the one or more top level IC dies. A plurality of conductive through-substrate vias (TSVs) each extend vertically through the supporting substrate. A metallic lid structure is disposed over the supporting substrate. The metallic lid structure is thermally coupled to the conductive TSVs.
    Type: Application
    Filed: September 14, 2023
    Publication date: November 28, 2024
    Inventors: Po-Yao Lin, Sing-Da Jiang, Tsunyen Wu, Shih-Wei Liu, Kathy Wei Yan
  • Publication number: 20240395663
    Abstract: A semiconductor device package provides for thermal considerations of a semiconductor die(s) through providing a thermal module. A substrate including an IC die disposed on the substrate is positioned between an upper plate and a lower plate of the thermal module. Heat pipes connect the upper plate and the lower plate. The thermal module allows for heat dissipation paths from the lower as well as upper plate. In some implementations, a liquid cooling plate is positioned between the substrate and the upper pate of the thermal module.
    Type: Application
    Filed: September 14, 2023
    Publication date: November 28, 2024
    Inventors: Sing-Da JIANG, Po-Yao LIN, Tsunyen WU, Shih-Wei LIU, Kathy Wei YAN
  • Publication number: 20240274504
    Abstract: A semiconductor package includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and including a vapor chamber base, the vapor chamber base including a plate portion, and an angled portion extending at an angle from opposing ends of the plate portion. A method of cooling the semiconductor package may include locating the semiconductor package in an immersion cooling chamber, immersing the semiconductor package in an immersion coolant in the immersion cooling chamber such that a plate portion and an angled portion of a vapor chamber base of the package lid is immersed in the immersion coolant, and transferring heat from the plate portion and angled portion of the vapor chamber base to the immersion coolant to cool the semiconductor package.
    Type: Application
    Filed: February 15, 2023
    Publication date: August 15, 2024
    Inventors: Po-Yao LIN, Yu-Chih LAI, Yu-Sheng LIN, Kathy Wei YAN
  • Publication number: 20240145433
    Abstract: A package structure includes a first die and a second die embedded in a first molding material, a first redistribution structure over the first die and the second die, a second molding material over portions of the first die and the second die, wherein the second molding material is disposed between a first portion of the first redistribution structure and a second portion of the first redistribution structure, a first via extending through the second molding material, wherein the first via is electrically connected to the first die, a second via extending through the second molding material, wherein the second via is electrically connected to the second die and a silicon bridge electrically coupled to the first via and the second via.
    Type: Application
    Filed: January 4, 2023
    Publication date: May 2, 2024
    Inventors: Po-Yao Lin, Chia-Hsiang Lin, Chien-Sheng Chen, Kathy Wei Yan
  • Patent number: 8362627
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Shripad Gokhale, Kathy Wei Yan, Bijay S. Saha, Samir Pandey, Ngoc K. Dang, Munehiro Toyama
  • Publication number: 20110084388
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 14, 2011
    Inventors: Shripad GOKHALE, Kathy Wei YAN, Bijay S. SAHA, Samir PANDEY, Ngoc K. DANG, Munehiro TOYAMA
  • Patent number: 7875503
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: January 25, 2011
    Assignee: Intel Corporation
    Inventors: Shripad Gokhale, Kathy Wei Yan, Bijay S. Saha, Samir Pandey, Ngoc K. Dang, Munehiro Toyama
  • Publication number: 20080157352
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Shripad Gokhale, Kathy Wei Yan, Bijay S. Saha, Samir Pandey, Ngoc K. Dang, Munehiro Toyama