Abstract: The present invention relates to a polishing method and a polishing apparatus for polishing a substrate, such as a wafer. The present invention further relates to a computer-readable storage medium storing a program for causing the polishing apparatus to perform the polishing method. The polishing method includes: rotating a polishing table (3); and polishing a substrate (W) by pressing the substrate (W) against a polishing surface (2a). Polishing the substrate (W) includes a film-thickness profile adjustment process and a polishing-end-point detection process. The film-thickness profile adjustment process includes adjusting pressing forces on the substrate (W) against the polishing surface (2a) based on a plurality of film thicknesses, and determining a point in time at which a film-thickness index value has reached a film-thickness threshold value. The film-thickness index value is determined from at least one of the plurality of film thicknesses.

Abstract: The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines.

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap.

Abstract: The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines.

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap.

Abstract: A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. The at least one protruding structure has a main portion of a first height and an upper portion on the main portion. The method also includes embedding the at least one protruding structure in a dielectric material. Further, the method includes removing at least an excess portion of the dielectric material, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material. In addition, the method includes forming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure.