Patents by Inventor Katie Qun Wang

Katie Qun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for through silicon via filling
    Patent number: 8722539
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: May 13, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey
  • PROCESS FOR THROUGH SILICON VIA FILLING
    Publication number: 20120031768
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Application
    Filed: October 11, 2011
    Publication date: February 9, 2012
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Wiley
  • Process for through silicon via filling
    Patent number: 8043967
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: October 25, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Wiley
  • Process for through silicon via filing
    Patent number: 7776741
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: August 17, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey
  • Process For Through Silicon Via Filling
    Publication number: 20100200412
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Application
    Filed: April 16, 2010
    Publication date: August 12, 2010
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Wiley
  • Process For Through Silicon Via Filing
    Publication number: 20100041226
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. Low copper concentration and high acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Application
    Filed: August 18, 2008
    Publication date: February 18, 2010
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey