Abstract: A semiconductor device includes: an insulating film provided on a back surface of a semiconductor substrate; a plurality of isolation regions provided to reach the insulating film from a main surface of the semiconductor substrate; at least a first semiconductor layer and a second semiconductor layer which are electrically insulated from each other by the isolation regions in the semiconductor substrate; a first voltage applied terminal electrically connected to a front surface of the first semiconductor layer; a second voltage applied terminal electrically connected to a front surface of the second semiconductor layer; a selector circuit receiving voltages from the first voltage applied terminal and the second voltage applied terminal, and supplying an output in accordance with a combination of the voltages; and a conductive layer provided so as to contact with the insulating film provided to the back side of the semiconductor substrate.

Abstract: A semiconductor device includes: an insulating film provided on a back surface of a semiconductor substrate; a plurality of isolation regions provided to reach the insulating film from a main surface of the semiconductor substrate; at least a first semiconductor layer and a second semiconductor layer which are electrically insulated from each other by the isolation regions in the semiconductor substrate; a first voltage applied terminal electrically connected to a front surface of the first semiconductor layer; a second voltage applied terminal electrically connected to a front surface of the second semiconductor layer; a selector circuit receiving voltages from the first voltage applied terminal and the second voltage applied terminal, and supplying an output in accordance with a combination of the voltages; and a conductive layer provided so as to contact with the insulating film provided to the back side of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate including a plurality of device regions and a device isolation region defining the device regions, and a semiconductor element located in a major surface of the semiconductor substrate and formed in at least one of the device regions. The device isolation region has a DTI (deep trench isolation) structure and has a bottom exposed to a backside of the semiconductor substrate.

Abstract: A method for fabricating a semiconductor device includes placing a semiconductor wafer on a stage, the semiconductor wafer having a plurality of ball-shaped external connecting terminals projected from a surface, bringing a probe card close to the semiconductor wafer placed on the stage to bring a plurality of probe terminals included in the probe card into contact with the external connecting terminals respectively, and applying a voltage to the semiconductor wafer through the probe terminal to perform a test of the semiconductor wafer. The probe terminals contact all the external connecting terminals.

Abstract: A method of manufacturing a semiconductor device includes the step of doping an N-type impurity via a selective region formed on a semiconductor substrate by lithography, the step of doping a P-type impurity in the semiconductor substrate subsequent to the doping step without forming a selective region by lithography, and the step of self-aligningly forming an N-diffusion layer and a P-diffusion layer by performing wet oxidation with respect to the semiconductor substrate in which the N-type impurity and the P-type impurity are doped.

Abstract: In the MOS FET semiconductor device having a LDD structure, a polysilicon layer of which a side wall film is formed is provided, the polysilicon layer is made conductive by doping an impurity by ion-implantation. The side wall film of conductive polysilicon can be used as a wiring by applying voltages to the end portions of the side wall film. The side wall film can be used not only as a wiring, but also as a resistor layer. The side wall film may be formed on the side surface of a resistor layer. The side wall film can be used as a wiring by doping impurity into the side wall film by ion-implantation so as to make the side wall film conductive. By virtue of these structures, the semiconductor chip in the semiconductor device can be reduced in size.

Abstract: A zapping diode concerned with a P-N junction diode provided in an integrated circuit, whose P-N junction is subjected to breakdown by an overvoltage to perform fine adjustment in the value of capacitance or resistance involved in the circuit. The diode has a first impurity region of a first conductivity type formed in a first conductivity type semiconductor region, a second impurity region, an interlayer insulation film formed over the semiconductor region, and a third conductor film formed on the semiconductor region between the first and second impurity region. The third conductor film, when applied by a reverse-bias voltage, controls the direction of breakdown in the P-N junction to thereby provide a consistent value of residual resistance.

Abstract: A first Al wire is connected to a gate electrode. On the first Al wire, an insulating film is provided. In the insulating film, an opening with a large cross-sectional area is made so as to correspond to the first Al wire. In the periphery of the opening, the insulating film is etched by RIE to make an opening. In the central area, the insulating film is etched by wet etching to make an opening. Inside the opening thus made, a second Al wire is formed. The second Al wire is connected to the first Al wire inside the opening. When the opening is made, the number of electrons trapped in the gate oxide film is small because the area etched by RIE is small. Since RIE etches the first Al wire deeper than wet etching, recesses are made around the first Al wire located inside the opening. The first and second Al wires are connected to each other via the recesses.

Abstract: An N-type buried region formed in the surface area of a semiconductor substrate is electrically connected to an N-type collector region formed in an epitaxial silicon layer on the semiconductor substrate. A P-type buried region is formed to overlap part of the N-type buried region. The P-type buried region is thick in the upward and downward directions of the N-type buried region. One end portion of the P-type buried region is electrically connected to a P-type base region and the other end portion thereof is electrically connected to a base region formed in the surface area of the semiconductor layer. The base region is applied with a base potential from the base region via the buried region. An N-type emitter region is formed in the base region. The N-type buried region and the P-type buried region are simultaneously formed by use of a difference between the diffusion coefficients of impurity.

Abstract: A first Al wire is connected to a gate electrode. On the first Al wire, an insulating film is provided. In the insulating film, an opening with a large cross-sectional area is made so as to correspond to the first Al wire. In the periphery of the opening, the insulating film is etched by RIE to make an opening. In the central area, the insulating film is etched by wet etching to make an opening. Inside the opening thus made, a second Al wire is formed. The second Al wire is connected to the first Al wire inside the opening. When the opening is made, the number of electrons trapped in the gate oxide film is small because the area etched by RIE is small. Since RIE etches the first Al wire deeper than wet etching, recesses are made around the first Al wire located inside the opening. The first and second Al wires are connected to each other via the recesses.

Abstract: An N channel type MOSFET is formed in a P type semiconductor substrate. A drain of the N channel type MOSFET is connected to a V.sub.DD line. A P.sup.- type impurity layer is formed in contact with the drain of the N channel type MOSFET. An input protection circuit is formed in the P type semiconductor substrate. The input protection circuit comprises a diode D.sub.1 in which a cathode is connected to an input terminal and an anode is connected to a V.sub.SS line, and a diode D.sub.2 in which a cathode is connected to the V.sub.DD line and an anode is connected to the V.sub.SS line. The anode of the diodes D.sub.1 and D.sub.2 comprises a P.sup.- type impurity layer. Impurity concentration of the P.sup.- type impurity layer the diodes D.sub.1 and D.sub.2 are higher than that of the P.sup.- impurity layer formed in contact with the drain of the N channel type MOSFET. The anode can be used in common to both diodes D.sub.1 and D.sub.2.