Patents by Inventor Katsuaki Masaki

Katsuaki Masaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240234141
    Abstract: A semiconductor substrate includes a support substrate, a mask pattern located above the support substrate and including a mask portion, a seed portion locally located in a layer above the support substrate in a plan view, and a semiconductor part including a GaN-based semiconductor and located above the mask pattern to be in contact with the seed portion and the mask portion.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 11, 2024
    Applicant: KYOCERA Corporation
    Inventors: Katsuaki MASAKI, Takeshi KAMIKAWA, Toshihiro KOBAYASHI, Yuichiro HAYASHI, Yuta AOKI
  • Publication number: 20240234137
    Abstract: A template substrate including a first seed region and a growth restricting region that are aligned in a first direction, and a first semiconductor part positioned above the template substrate are provided, the first semiconductor part includes a first base positioned above the first seed region, and a first wing connected to the first base, the first wing facing the growth restricting region with a first void space interposed therebetween, the first wing includes an edge positioned above the growth restricting region, and a ratio of a width of the first void space with respect to a thickness of the first void space in the first direction is equal to or larger than 5.0.
    Type: Application
    Filed: October 19, 2022
    Publication date: July 11, 2024
    Applicant: KYOCERA CORPORATION
    Inventors: Takeshi KAMIKAWA, Yuta AOKI, Kazuma TAKEUCHI, Katsuaki MASAKI, Fumio YAMASHITA
  • Publication number: 20240203732
    Abstract: A main substrate, a seed portion (SD) located higher than the main substrate, and first and second semiconductor parts (8F and 8S) arranged side by side in a first direction (9Y direction) are provided. The first and second semiconductor parts are in contact with the seed portion, a longitudinal direction of the seed portion (SD) is the first direction (Y direction), and a hollow portion (VD) is located between the main substrate (1) and each of the first semiconductor part and the second semiconductor part.
    Type: Application
    Filed: April 14, 2022
    Publication date: June 20, 2024
    Applicant: KYOCERA Corporation
    Inventors: Katsuaki MASAKI, Takeshi KAMIKAWA, Toshihiro KOBAYASHI, Yuichiro HAYASHI, Yuki TANIGUCHI, Yuta AOKI
  • Publication number: 20240136181
    Abstract: A semiconductor substrate includes a support substrate, a mask pattern located above the support substrate and including a mask portion, a seed portion locally located in a layer above the support substrate in a plan view, and a semiconductor part including a GaN-based semiconductor and located above the mask pattern to be in contact with the seed portion and the mask portion.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Applicant: KYOCERA Corporation
    Inventors: Katsuaki MASAKI, Takeshi KAMIKAWA, Toshihiro KOBAYASHI, Yuichiro HAYASHI, Yuta AOKI
  • Publication number: 20240136177
    Abstract: A template substrate including a first seed region and a growth restricting region that are aligned in a first direction, and a first semiconductor part positioned above the template substrate are provided, the first semiconductor part includes a first base positioned above the first seed region, and a first wing connected to the first base, the first wing facing the growth restricting region with a first void space interposed therebetween, the first wing includes an edge positioned above the growth restricting region, and a ratio of a width of the first void space with respect to a thickness of the first void space in the first direction is equal to or larger than 5.0.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Applicant: KYOCERA CORPORATION
    Inventors: Takeshi KAMIKAWA, Yuta AOKI, Kazuma TAKEUCHI, Katsuaki MASAKI, Fumio YAMASHITA
  • Publication number: 20240072198
    Abstract: A semiconductor substrate includes a heterogeneous substrate, a mask layer having an opening portion and a mask portion, a seed portion overlapping the opening portion, and a semiconductor layer including a GaN-based semiconductor and disposed on the seed portion and the mask portion. An upper surface of an effective portion of the semiconductor layer includes at least one low-level defective region with a size of 10 ?m in a first direction along a width direction of the opening portion and 10 ?m in a second direction orthogonal to the first direction, and a line defect is not measured by a CL method in the low-level defective region.
    Type: Application
    Filed: December 28, 2021
    Publication date: February 29, 2024
    Applicant: KYOCERA Corporation
    Inventors: Takeshi KAMIKAWA, Katsuaki MASAKI, Toshihiro KOBAYASHI, Yuichiro HAYASHI
  • Publication number: 20230335400
    Abstract: A method for producing a semiconductor device includes: preparing a template substrate including an underlying substrate and a mask including an opening portion and a mask portion; forming a first semiconductor portion from above the opening portion over a first region of the mask portion; and forming a second semiconductor portion located above the first semiconductor portion and containing gallium and aluminum, and a third semiconductor portion located on a second region of the mask portion where the first semiconductor portion is not formed and containing aluminum.
    Type: Application
    Filed: June 22, 2021
    Publication date: October 19, 2023
    Applicant: KYOCERA Corporation
    Inventor: Katsuaki MASAKI
  • Publication number: 20230326993
    Abstract: A method of manufacturing a semiconductor element includes forming a mask on a front surface of a substrate, the mask having an opening to expose the front surface; growing a first semiconductor layer by epitaxially growing a semiconductor along the mask, starting from the front surface exposed through the opening, and growing a second semiconductor layer on a surface of the first semiconductor layer located opposite to the substrate in a layering direction, and providing an electrode on a surface of the second semiconductor layer located opposite to the surface of the first semiconductor layer in the layering direction. A width from an end portion of the surface to the electrode is smaller than a width of the mask.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 12, 2023
    Applicant: KYOCERA Corporation
    Inventors: Katsunori AZUMA, Katsuaki MASAKI, Kokichi FUJITA, Yuichiro HAYASHI, Tomohisa HIRAYAMA, Tatsuro SAWADA, hAYAO kasai
  • Publication number: 20230140914
    Abstract: A method of manufacturing a semiconductor element includes: forming a first semiconductor layer (SL1) and a second semiconductor layer (SL2) larger in thickness than the first semiconductor layer (SL1) on a mask layer (ML) including a first opening portion (K1) and a second opening portion (K2); forming a first device layer (DL1) and a second device layer (DL2); and bonding the first device layer (DL1) and the second device layer (DL2) to a support substrate (SK).
    Type: Application
    Filed: March 29, 2021
    Publication date: May 11, 2023
    Applicant: KYOCERA Corporation
    Inventors: Katsuaki MASAKI, Masahiro ARAKI
  • Publication number: 20220415714
    Abstract: Included are: an underlying substrate including a first surface; a semiconductor element layer dividable into a plurality of element portions, the semiconductor element layer being located on the first surface of the underlying substrate; and a support substrate including a second surface on which the semiconductor element layer is located, the second surface facing the first surface, the semiconductor element layer being located on the second surface. The support substrate and the semiconductor element layer include a weak portion used to divide the semiconductor element layer into the plurality of element portions.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 29, 2022
    Applicant: KYOCERA Corporation
    Inventors: Kentaro MURAKAWA, Katsuaki MASAKI
  • Publication number: 20220376132
    Abstract: A method for manufacturing a semiconductor element of the present disclosure includes: a step of preparing a substrate; a first element forming step of forming a first semiconductor layer in a first region on a surface of the substrate; a first element separating step of separating the first semiconductor layer from the substrate; and a second element forming step of forming a second semiconductor layer in a second region on the surface of the substrate from which the first semiconductor layer is separated. Additionally, in the method for manufacturing a semiconductor element of the present disclosure, at least a portion of the second region overlaps the first region.
    Type: Application
    Filed: September 30, 2020
    Publication date: November 24, 2022
    Applicant: KYOCERA CORPORATION
    Inventors: Takehiro NISHIMURA, Yutaka KUBA, Katsuaki MASAKI, Kentaro MURAKAWA, Toshihiro KOBAYASHI
  • Publication number: 20220140179
    Abstract: A method of manufacturing a semiconductor element according to the present disclosure includes an element forming step (S1) of forming, on an underlying substrate (11), a semiconductor element (15) connected to the underlying substrate (11) via a connecting portion (13b) and including an upper surface (15a) inclined with respect to a growth surface of the underlying substrate (11), a preparing step (S2) of preparing a support substrate (16) including an opposing surface (16c) facing the underlying substrate (11), a bonding step (S3) of pressing the upper surface (15a) of the semiconductor element (15) against the opposing surface (16c) of the support substrate (16) and heating the upper surface (15a) to bond the upper surface (15a) of the semiconductor element (15) to the support substrate (16), and a peeling step (S4) of peeling the semiconductor element (15) from the underlying substrate (11).
    Type: Application
    Filed: February 28, 2020
    Publication date: May 5, 2022
    Inventors: Katsuaki MASAKI, Kentaro MURAKAWA
  • Publication number: 20220069185
    Abstract: The present disclosure relates to an electronic component joining method and a joined structure. A solder layer made of a gold-tin alloy including 20 mass % or greater of tin is formed on a light-emitting element side, and a layer including gold as a main component is formed, as a joining layer for joining to the solder layer, on a submount side. The solder layer and the joining layer are heated at a temperature below the melting point of the gold-tin alloy of the solder layer to join the light-emitting element and the submount.
    Type: Application
    Filed: December 26, 2019
    Publication date: March 3, 2022
    Inventors: Kentaro MURAKAWA, Katsuaki MASAKI
  • Patent number: 10862264
    Abstract: A light-emitting element housing member includes a substrate that is made of a ceramic and internally includes a deep-bottom-type space portion having an opening in at least one position thereof, wherein an inner wall of the space portion serves as a mounting part for a light-emitting element. A light-emitting element housing member includes a mounting part meant for mounting a light-emitting element and includes a substrate that includes a bottom base material having a rectangular shape in a planar view and a wall member provided on the bottom base material to enclose the mounting part in a U-shaped manner and have an opening in at least one portion thereof, wherein the substrate is integrally formed of a ceramic.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 8, 2020
    Assignee: KYOCERA Corporation
    Inventors: Youji Furukubo, Sentaro Yamamoto, Masanori Okamoto, Katsuaki Masaki, Takehiro Nishimura, Kazuya Shibata
  • Patent number: 10443149
    Abstract: A method of producing a crystal includes a step of preparing a solution containing carbon and a silicon solvent, and a seed crystal of silicon carbide; a step of contacting a lower face of the seed crystal with the solution; a step of raising a temperature of the solution to a first temperature zone; a step of relatively elevating the seed crystal with respect to the solution in a state where a temperature of the solution is being lowered from the first temperature zone to a second temperature zone; a step of raising a temperature of the solution from the second temperature zone to the first temperature zone; and a step of relatively elevating the seed crystal with respect to the solution in a state where a temperature of the solution is being lowered from the first temperature zone to the second temperature zone.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: October 15, 2019
    Assignee: KYOCERA Corporation
    Inventors: Chiaki Domoto, Yutaka Kuba, Katsuaki Masaki, Yuuichiro Hayashi
  • Publication number: 20190131765
    Abstract: A light-emitting element housing member includes a substrate that is made of a ceramic and internally includes a deep-bottom-type space portion having an opening in at least one position thereof, wherein an inner wall of the space portion serves as a mounting part for a light-emitting element. A light-emitting element housing member includes a mounting part meant for mounting a light-emitting element and includes a substrate that includes a bottom base material having a rectangular shape in a planar view and a wall member provided on the bottom base material to enclose the mounting part in a U-shaped manner and have an opening in at least one portion thereof, wherein the substrate is integrally formed of a ceramic.
    Type: Application
    Filed: April 18, 2017
    Publication date: May 2, 2019
    Applicant: KYOCERA Corporation
    Inventors: Youji FURUKUBO, Sentaro YAMAMOTO, Masanori OKAMOTO, Katsuaki MASAKI, Takehiro NISHIMURA, Kazuya SHIBATA
  • Patent number: 10151045
    Abstract: A method for producing a crystal, according to the present invention, where the lower surface 4B of a seed crystal 4 which is rotatably arranged and made of silicon carbide is brought into contact with a solution 5 of silicon solvent containing carbon in a crucible 6 which is rotatably arranged and the seed crystal 4 is pulled up and a crystal of silicon carbide is grown from the solution 5 on the lower surface 4B of the seed crystal 4, comprising the steps of bringing the lower surface 4B of the seed crystal 4 into contact with the solution 5 in a contact step, rotating the seed crystal 4 in a seed crystal rotation step, rotating the crucible 6 in a crucible rotation step, and stopping rotation of the crucible 6, while the seed crystal 4 is rotated in the state in which the lower surface 4B of the seed crystal 4 is in contact with the solution 5, in a deceleration step.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: December 11, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Chiaki Domoto, Katsuaki Masaki, Yutaka Kuba, Daisuke Ueyama, Kouji Miyamoto, Yuuichiro Hayashi
  • Publication number: 20180171506
    Abstract: A seed crystal holder according to the present invention for growing a crystal by a solution method, and that includes a seed crystal made of silicon carbide; a holding member above the seed crystal; a bonding agent configured to fix the seed crystal and the holding member; and a sheet member made of carbon which is interposed in the bonding agent in a thickness direction, and which has an outer periphery smaller than an outer periphery of the seed crystal in a plan view.
    Type: Application
    Filed: January 18, 2018
    Publication date: June 21, 2018
    Inventors: Katsuaki MASAKI, Yutaka KUBA, Chiaki DOMOTO, Daisuke UEYAMA, Yuichiro HAYASHI
  • Patent number: 9890470
    Abstract: A seed crystal holder according to the present invention for growing a crystal by a solution method, and that includes a seed crystal made of silicon carbide; a holding member above the seed crystal; a bonding agent configured to fix the seed crystal and the holding member; and a sheet member made of carbon which is interposed in the bonding agent in a thickness direction, and which has an outer periphery smaller than an outer periphery of the seed crystal in a plan view.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 13, 2018
    Assignee: KYOCERA Corporation
    Inventors: Katsuaki Masaki, Yutaka Kuba, Chiaki Domoto, Daisuke Ueyama, Yuichiro Hayashi
  • Publication number: 20180016703
    Abstract: A method for producing a crystal of silicon carbide includes a preparation step, a contact step, a start step, a first growth step, a cooling step, and a second growth step.
    Type: Application
    Filed: January 26, 2016
    Publication date: January 18, 2018
    Inventors: Chiaki DOMOTO, Katsuaki MASAKI, Yutaka KUBA