Patents by Inventor Katsuaki Matsufuji

Katsuaki Matsufuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Recording apparatus including a plurality of EEPROMS where parallel accessing is used
    Patent number: 5761702
    Abstract: A recording apparatus includes a plurality of EEPROMs. For example, one of the EEPROMs is for main recording and other EEPROMs are for standby recording. These EEPROMs include two recording regions which can be erased independently from each other. The erasing and writing from the respective EEPROMs can be done at the same time in parallel operation, thus enabling recording by eliminating a waiting time for erasure.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: June 2, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsuaki Matsufuji
  • Digital PLL circuit
    Patent number: 5661425
    Abstract: A phase control circuit adjusts the width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK is in synchronization with an EFM signal. A velocity detector detects offset in velocity by counting a pulse width of an EFM signal with a master clock signal MCK. The phase control circuit alters the pulse width of a PLL clock signal according to the detected offset in velocity to alter the average frequency of a PLL clock signal in proportion to offset of the rotational speed.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: August 26, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidenori Minoda, Hiroyuki Matsuoka, Katsuaki Matsufuji