Patents by Inventor Katsuaki Onoda
Katsuaki Onoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060177077Abstract: A high frequency mixer circuit is used as a down converter in which an RF signal and an LO signal are mixed to generate an IF signal, or as an up converter in which an IF signal and an LO signal are mixed to generate an RF signal. The high frequency mixer circuit has a wiring layout wherein wiring lines for propagating LO signals intersect only one of the wiring lines for propagating RF signals or IF signals.Type: ApplicationFiled: February 9, 2006Publication date: August 10, 2006Applicant: Sanyo Electric Co., Ltd.Inventors: Yasuyuki Okada, Akihito Nagamatsu, Katsuaki Onoda, Shigehiro Nakamura, Mikito Sakakibara
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Publication number: 20050179106Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: April 12, 2005Publication date: August 18, 2005Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6787871Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: GrantFiled: October 30, 2002Date of Patent: September 7, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6777277Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: August 17, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6682968Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: January 27, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6628174Abstract: An impedance transformer is so designed that the impedance and the reactance of a tuning part reach zero at a central control voltage. An open stub is employed for setting the characteristic impedance of a tuning stub to the minimum value when a variable reactance circuit is inductive while setting the characteristic impedance to −1.22 times the reactance of the variable reactance circuit when the variable reactance circuit is capacitive. A short stub is employed for setting the characteristic impedance of the tuning stub to 0.82 times the reactance of the variable reactance circuit when the variable reactance is inductive, while setting the characteristic impedance to the maximum when the variable reactance circuit is capacitive.Type: GrantFiled: November 6, 2001Date of Patent: September 30, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Toshikazu Imaoka, Katsuaki Onoda
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Publication number: 20030094668Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: ApplicationFiled: October 30, 2002Publication date: May 22, 2003Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030036252Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 20, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030025175Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 6, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20020093388Abstract: An impedance transformer is so designed that the impedance and the reactance of a tuning part reach zero at a central control voltage. An open stub is employed for setting the characteristic impedance of a tuning stub to the minimum value when a variable reactance circuit is inductive while setting the characteristic impedance to −1.22 times the reactance of the variable reactance circuit when the variable reactance circuit is capacitive. A short stub is employed for setting the characteristic impedance of the tuning stub to 0.82 times the reactance of the variable reactance circuit when the variable reactance is inductive, while setting the characteristic impedance to the maximum when the variable reactance circuit is capacitive.Type: ApplicationFiled: November 6, 2001Publication date: July 18, 2002Inventors: Toshikazu Imaoka, Katsuaki Onoda