Abstract: A semiconductor storage device includes a first region including a level shifter, a second region including a level shifter, a power input pad, and an internal power generation circuit configured to generate an internal power supply voltage using a first power supply voltage supplied through the power input pad and supply the internal power supply voltage to the first and second regions. The internal power generation circuit separately transmits a first signal to the level shifter of the first region for triggering a start of a first operation of the first region and a second signal to the level shifter of the second region for triggering a start of a second operation of the second region.

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell, a first word line coupled between a control end of the memory cell and a first node, a resistance element coupled between the first node and a second node, a control circuit configured to output a voltage to the second node, a first switch coupled between the first node and a third node, a second switch coupled between the second node and the third node, and a comparator including an input end that receives a signal corresponding to a voltage of the third node.

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell, a first word line coupled between a control end of the memory cell and a first node, a resistance element coupled between the first node and a second node, a control circuit configured to output a voltage to the second node, a first switch coupled between the first node and a third node, a second switch coupled between the second node and the third node, and a comparator including an input end that receives a signal corresponding to a voltage of the third node.

Abstract: A discharge circuit includes first and second transistors of a first polarity, third and fourth transistors of a second polarity, and first and second current sources having first ends electrically connected to first end of the third transistor and first end of the fourth transistor, respectively, and second ends supplied with a first voltage. First end of the first transistor is supplied with a second voltage higher than the first voltage. First end of the second transistor is electrically separated from the first end of the first transistor. Gate and second end of the first transistor, gate of the second transistor, and second end of the third transistor are electrically connected to one another. Second end of the second transistor, gate of the third transistor, and second end and gate of the fourth transistor are electrically connected to one another.

Abstract: A discharge circuit includes first and second transistors of a first polarity, third and fourth transistors of a second polarity, and first and second current sources having first ends electrically connected to first end of the third transistor and first end of the fourth transistor, respectively, and second ends supplied with a first voltage. First end of the first transistor is supplied with a second voltage higher than the first voltage. First end of the second transistor is electrically separated from the first end of the first transistor. Gate and second end of the first transistor, gate of the second transistor, and second end of the third transistor are electrically connected to one another. Second end of the second transistor, gate of the third transistor, and second end and gate of the fourth transistor are electrically connected to one another.

Abstract: A semiconductor memory device includes a first comparative device, to which first and second voltages are input; a first capacitor, which accumulates the electrical potential of a first node; a power source, which outputs the first electric current to a second node; a resistor, which generates a third voltage in the second node; a second capacitor, which accumulates the electric potential of the second node; first switches, which make a common connection at a third node possible for the first node and the second node, to which the first capacitor and the second capacitor are connected respectively; and a second comparison device, which uses as an input voltage a fourth voltage, which is obtained as a result of the charge share between the first and the second capacitors and the electrical potential of a fourth node, and equalizes the electrical potential of the fourth node with the fourth voltage.

Abstract: A semiconductor memory device includes a memory cell array in which memory cells are arranged, and a first wiring connected to the memory cells. A discharging circuit discharges the voltage of the first wiring according to a first current. In addition, a charging circuit charges the voltage of the first wiring according to a second current. A control circuit detects the voltage of the first wiring and controls a magnitude of the second current based on the detected voltage. A current detection unit generates a third current proportional to the second current and generates a detection result based on a magnitude of the third current. The discharging circuit is configured to control a magnitude of the first current in accordance with the detection result.

Abstract: A semiconductor memory device includes a memory cell array in which memory cells are arranged, and a first wiring connected to the memory cells. A discharging circuit discharges the voltage of the first wiring according to a first current. In addition, a charging circuit charges the voltage of the first wiring according to a second current. A control circuit detects the voltage of the first wiring and controls a magnitude of the second current based on the detected voltage. A current detection unit generates a third current proportional to the second current and generates a detection result based on a magnitude of the third current. The discharging circuit is configured to control a magnitude of the first current in accordance with the detection result.

Abstract: A semiconductor memory device includes a first comparative device, to which first and second voltages are input; a first capacitor, which accumulates the electrical potential of a first node; a power source, which outputs the first electric current to a second node; a resistor, which generates a third voltage in the second node; a second capacitor, which accumulates the electric potential of the second node; first switches, which make a common connection at a third node possible for the first node and the second node, to which the first capacitor and the second capacitor are connected respectively; and a second comparison device, which uses as an input voltage a fourth voltage, which is obtained as a result of the charge share between the first and the second capacitors and the electrical potential of a fourth node, and equalizes the electrical potential of the fourth node with the fourth voltage.

Abstract: According to one embodiment, a resistance-change memory includes a memory element in which its variable resistance state corresponds to data to be stored therein, a pulse generation circuit which generates a first pulse, a second pulse, a third pulse, and a fourth pulse, the first pulse having a first amplitude which changes the resistance state of the memory element from a high- to a low-resistance state, the third pulse having a third amplitude smaller than the first amplitude to read data in the memory element, the fourth pulse having a fourth amplitude between the first amplitude and the third amplitude, and a control circuit which controls the operations of the memory element and the pulse generation circuit. The control circuit supplies the fourth pulse to the memory element after supplying the first pulse to the memory element.

Abstract: According to one embodiment, a semiconductor memory device includes memory cell units including serially-connected memory cells, which includes a semiconductor pillar and conductive and insulation films surrounding the semiconductor pillar. The memory cell units constitute blocks each of which is the minimum unit of data erasure. A pipe layer in at least one pair of adjacent first and second memory cell units of the memory cell units includes a semiconductor layer connected to the semiconductor pillars in the first and second memory cell units, and are connected to first ends of the first and second memory cell units. A conductive plate between the first ends of the first and second memory cell units and the semiconductor substrate contain the pipe layers of at least two blocks and controls conduction of the pipe layers. A supply path structure is connected to the plate and transmitting a potential the plate.

Abstract: According to one embodiment, a semiconductor memory device includes memory cell units including serially-connected memory cells, which includes a semiconductor pillar and conductive and insulation films surrounding the semiconductor pillar. The memory cell units constitute blocks each of which is the minimum unit of data erasure. A pipe layer in at least one pair of adjacent first and second memory cell units of the memory cell units includes a semiconductor layer connected to the semiconductor pillars in the first and second memory cell units, and are connected to first ends of the first and second memory cell units. A conductive plate between the first ends of the first and second memory cell units and the semiconductor substrate contain the pipe layers of at least two blocks and controls conduction of the pipe layers. A supply path structure is connected to the plate and transmitting a potential the plate.

Abstract: According to one embodiment, a resistance-change memory includes a memory element in which its variable resistance state corresponds to data to be stored therein, a pulse generation circuit which generates a first pulse, a second pulse, a third pulse, and a fourth pulse, the first pulse having a first amplitude which changes the resistance state of the memory element from a high- to a low-resistance state, the third pulse having a third amplitude smaller than the first amplitude to read data in the memory element, the fourth pulse having a fourth amplitude between the first amplitude and the third amplitude, and a control circuit which controls the operations of the memory element and the pulse generation circuit. The control circuit supplies the fourth pulse to the memory element after supplying the first pulse to the memory element.