Patents by Inventor Katsuhiko Akao

Katsuhiko Akao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7911063
    Abstract: In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML30 and ML37 located on the fourth interconnection layer are extended. Thus, even in a case where a stress is applied from outside to bonding pads BP1 and BP2 located above, the stress is wholly dispersed by the third interconnection layers and the fourth interconnection layer which are laminated to intersect with each other, and stress concentration on a particular point can be relieved to restrain deterioration in semiconductor device strength to a minimum. Accordingly, it is possible to provide the semiconductor device having a structure in which productivity of the semiconductor device can be improved while the stress concentration applied from outside on the particular point of the bonding pad is relieved.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Terazono, Katsuhiko Akao
  • Publication number: 20090146313
    Abstract: In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML30 and ML37 located on the fourth interconnection layer are extended. Thus, even in a case where a stress is applied from outside to bonding pads BP1 and BP2 located above, the stress is wholly dispersed by the third interconnection layers and the fourth interconnection layer which are laminated to intersect with each other, and stress concentration on a particular point can be relieved to restrain deterioration in semiconductor device strength to a minimum. Accordingly, it is possible to provide the semiconductor device having a structure in which productivity of the semiconductor device can be improved while the stress concentration applied from outside on the particular point of the bonding pad is relieved.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 11, 2009
    Inventors: Shinichi Terazono, Katsuhiko Akao