Abstract: A voltage regulator and a corresponding method of regulating a voltage are presented. The voltage regulator includes an N-type power switch, an error amplifier, and a switch capacitor circuit. The switch capacitor circuit includes a first capacitor coupled to a network of switches, the switch capacitor circuit has a first port coupled to an output the error amplifier, a second port coupled to an output terminal of the power switch, and a third port coupled to a control terminal of the power switch. The switch capacitor circuit is iteratively operable between a first phase and a second phase. In the first phase the first port is coupled to ground via a path comprising the first capacitor, and in the second phase the second port is coupled to the third port via a path comprising the first capacitor. The voltage regulator may be implemented as a low dropout regulator.

Abstract: It is an object of one or more embodiments of the present disclosure to provide a battery charger with a constant current control loop, for use in linear and switching chargers. Advantages include digital controls and a comparator, for decreasing charging current towards termination. The technique of the disclosure eliminates a constant voltage loop and amplifier, without increasing charging time. The technique also simplifies porting the design to another process technology node, and reduces size.

Abstract: It is an object of one or more embodiments of the present disclosure to provide a battery charger with a constant current control loop, for use in linear and switching chargers. Advantages include digital controls and a comparator, for decreasing charging current towards termination. The technique of the disclosure eliminates a constant voltage loop and amplifier, without increasing charging time. The technique also simplifies porting the design to another process technology node, and reduces size.

Abstract: This solid-state imaging device 100 has: a photosensitive part that includes pixel portions 211, which are disposed in a matrix, and charge transfer parts 212 for transferring, by the column, the signal charge of the pixel portions; a plurality of charge storage parts 220 that accumulate the signal charges transferred by the plurality of charge transfer parts of the photosensitive part; a relay part 240 that relays the transfer of the signal charges transferred by the plurality of charge transfer parts to each charge storage part; an output part 230 that outputs the signal charges of the plurality of charge storage parts as electric signals; a first substrate 110 at which the photosensitive unit 210 is formed; and a second substrate 120 at which the charge storage part 220 and output unit 230 are formed.

Abstract: A solid state imaging device has: a photosensitive part containing a plurality of charge transfer parts that transfer, in column units, the signal charges of a plurality of photoelectric conversion elements disposed in a matrix; a conversion/output unit that converts, to an electrical signal, the signal charges forwarded by the charge transfer parts; a peripheral circuit part that performs a predetermined process with respect to the electrical signals from the conversion/output part; a relay part that relays the forwarding to the peripheral circuit part of the electrical signal from the conversion/output part; a first substrate where a photosensitive part and the conversion/output part are formed; and a second substrate where the peripheral circuit part is formed. The first and second substrates are stacked together, and the relay part electrically connects the conversion/output part formed at the first substrate to the peripheral circuit part formed at the second substrate.

Abstract: A solid state imaging device has: a photosensitive part containing a plurality of charge transfer parts that transfer, in column units, the signal charges of a plurality of photoelectric conversion elements disposed in a matrix; a conversion/output unit that converts, to an electrical signal, the signal charges forwarded by the charge transfer parts; a peripheral circuit part that performs a predetermined process with respect to the electrical signals from the conversion/output part; a relay part that relays the forwarding to the peripheral circuit part of the electrical signal from the conversion/output part; a first substrate where a photosensitive part and the conversion/output part are formed; and a second substrate where the peripheral circuit part is formed. The first and second substrates are stacked together, and the relay part electrically connects the conversion/output part formed at the first substrate to the peripheral circuit part formed at the second substrate.

Abstract: This solid-state imaging device 100 has: a photosensitive part that includes pixel portions 211, which are disposed in a matrix, and charge transfer parts 212 for transferring, by the column, the signal charge of the pixel portions; a plurality of charge storage parts 220 that accumulate the signal charges transferred by the plurality of charge transfer parts of the photosensitive part; a relay part 240 that relays the transfer of the signal charges transferred by the plurality of charge transfer parts to each charge storage part; an output part 230 that outputs the signal charges of the plurality of charge storage parts as electric signals; a first substrate 110 at which the photosensitive unit 210 is formed; and a second substrate 120 at which the charge storage part 220 and output unit 230 are formed.

Abstract: Pipeline analog-to-digital converters (ADCs) are used in many applications, but because of the configuration, components may be idled, which wastes power. Here, an ADC is provided that enables one or more stages to be switched off during a power conservation mode. By using switch networks, the ADC can produce accurate results with reduced power consumption, as desired.

Abstract: Pipeline analog-to-digital converters (ADCs) are used in many applications, but because of the configuration, components may be idled, which wastes power. Here, an ADC is provided that enables one or more stages to be switched off during a power conservation mode. By using switch networks, the ADC can produce accurate results with reduced power consumption, as desired.

Abstract: A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and generates a second delay signal. A control circuit controls the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical. A generation circuit combines the first edge of the first delay signal and the second edge of the second delay signal, and generates a third delay signal.

Abstract: A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and generates a second delay signal. A control circuit controls the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical. A generation circuit combines the first edge of the first delay signal and the second edge of the second delay signal, and generates a third delay signal.

Abstract: The analog-to-digital converter directly acquires a supplied clock signal, generates a current control signal depending on the sampling frequency of the clock signal, so as to control a current value. Thus, it becomes possible to control the current to an optimal value according to the sampling frequency, irrespective of the clock signal generation means, achieving low power consumption in the analog-to-digital converter.

Abstract: The analog-to-digital converter directly acquires a supplied clock signal, generates a current control signal depending on the sampling frequency of the clock signal, so as to control a current value. Thus, it becomes possible to control the current to an optimal value according to the sampling frequency, irrespective of the clock signal generation means, achieving low power consumption in the analog-to-digital converter.