Patents by Inventor Katsuhiko Fukasaku
Katsuhiko Fukasaku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014326Abstract: A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.Type: ApplicationFiled: September 25, 2023Publication date: January 11, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Katsuhiko FUKASAKU
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Patent number: 11804554Abstract: A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.Type: GrantFiled: June 1, 2022Date of Patent: October 31, 2023Assignee: Sony Semiconductor Solutions CorporationInventor: Katsuhiko Fukasaku
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Patent number: 11476350Abstract: [Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control. [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.Type: GrantFiled: May 31, 2018Date of Patent: October 18, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Katsuhiko Fukasaku, Shinichi Miyake
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Publication number: 20220302322Abstract: A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.Type: ApplicationFiled: June 1, 2022Publication date: September 22, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Katsuhiko FUKASAKU
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Patent number: 11393931Abstract: A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode A further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.Type: GrantFiled: August 14, 2019Date of Patent: July 19, 2022Assignee: Sony Semiconductor Solutions CorporationInventor: Katsuhiko Fukasaku
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Patent number: 11276753Abstract: A transistor and electronic apparatus are disclosed. In one example, a transistor includes a semiconductor substrate containing an electrically-conductive impurity. A device separation layer defines a device region. A buried insulation layer is provided in the device region, and a gate electrode crosses the device region. A drain region and a source region are opposed to each other with the gate electrode in between in the device region. A concentration or a polarity of the electrically-conductive impurity in the semiconductor substrate in an end region including at least an end portion of the gate electrode on drain region side is different from a concentration or a polarity of the electrically-conductive impurity in the semiconductor substrate in a middle region including a middle portion of the gate electrode.Type: GrantFiled: June 15, 2018Date of Patent: March 15, 2022Assignee: Sony Semiconductor Solutions CorporationInventor: Katsuhiko Fukasaku
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Publication number: 20210391366Abstract: A semiconductor device according to an aspect of the present technology includes a low-concentration N-type region, a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction, which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked, a first insulating film placed between the gate electrode and the low-concentration N-type region, and a second insulating film placed between the gate electrode and the first high-concentration N-type region. The first high-concentration N-type region is connected to one of a source electrode and a drain electrode. The second high-concentration N-type region is connected to the other of the source electrode and the drain electrode.Type: ApplicationFiled: October 2, 2019Publication date: December 16, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Katsuhiko FUKASAKU, Koichi MATSUMOTO, Akito SHIMIZU
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Publication number: 20210167224Abstract: A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode A further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.Type: ApplicationFiled: August 14, 2019Publication date: June 3, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Katsuhiko FUKASAKU
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Publication number: 20200235205Abstract: A transistor and electronic apparatus are disclosed. In one example, a transistor includes a semiconductor substrate containing an electrically-conductive impurity. A device separation layer defines a device region. A buried insulation layer is provided in the device region, and a gate electrode crosses the device region. A drain region and a source region are opposed to each other with the gate electrode in between in the device region. A concentration or a polarity of the electrically-conductive impurity in the semiconductor substrate in an end region including at least an end portion of the gate electrode on drain region side is different from a concentration or a polarity of the electrically-conductive impurity in the semiconductor substrate in a middle region including a middle portion of the gate electrode.Type: ApplicationFiled: June 15, 2018Publication date: July 23, 2020Inventor: Katsuhiko Fukasaku
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Publication number: 20200161469Abstract: [Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control. [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.Type: ApplicationFiled: May 31, 2018Publication date: May 21, 2020Inventors: Katsuhiko Fukasaku, Shinichi Miyake
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Patent number: 10522357Abstract: Both an improvement of on-current and suppression of leakage current of a transistor are achieved. A transistor includes a drain, a source, a gate, and a gate insulating film. In the transistor, the gate insulating film is disposed between the source and the drain. In addition, in the transistor, the gate has a plurality of regions provided on a surface of the gate insulating film. In addition, in the gate, the plurality of regions provided on the gate insulating film have different work functions.Type: GrantFiled: December 10, 2015Date of Patent: December 31, 2019Assignee: Sony Semiconductor Solutions CorporationInventors: Katsuhiko Fukasaku, Takaaki Tatsumi
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Patent number: 10468403Abstract: The present technology relates to a semiconductor integrated circuit which operates with a low voltage and is capable of preventing destruction of a protection circuit and a control method thereof. The semiconductor integrated circuit includes a resistance element and a capacitance element connected between a power supply line and a ground line in series, an inverter of which an input is connected between the resistance element and the capacitance element, a MOS transistor of which a gate electrode is connected to an output of the inverter and a drain electrode and a source electrode are respectively connected to the power supply line and the ground line, and a current limit element inserted between a well region where the MOS transistor is formed and the gate electrode. The present technology is applied to, for example, the protection circuit for preventing destruction of an internal circuit by ESD and the like.Type: GrantFiled: December 22, 2016Date of Patent: November 5, 2019Assignee: Sony CorporationInventors: Katsuhiko Fukasaku, Daisuke Nakagawa
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Publication number: 20180374840Abstract: The present technology relates to a semiconductor integrated circuit which operates with a low voltage and is capable of preventing destruction of a protection circuit and a control method thereof. The semiconductor integrated circuit includes a resistance element and a capacitance element connected between a power supply line and a ground line in series, an inverter of which an input is connected between the resistance element and the capacitance element, a MOS transistor of which a gate electrode is connected to an output of the inverter and a drain electrode and a source electrode are respectively connected to the power supply line and the ground line, and a current limit element inserted between a well region where the MOS transistor is formed and the gate electrode. The present technology is applied to, for example, the protection circuit for preventing destruction of an internal circuit by ESD and the like.Type: ApplicationFiled: December 22, 2016Publication date: December 27, 2018Applicant: Sony CorporationInventors: Katsuhiko FUKASAKU, Daisuke NAKAGAWA
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Publication number: 20180240673Abstract: Both an improvement of on-current and suppression of leakage current of a transistor are achieved. A transistor includes a drain, a source, a gate, and a gate insulating film. In the transistor, the gate insulating film is disposed between the source and the drain. In addition, in the transistor, the gate has a plurality of regions provided on a surface of the gate insulating film. In addition, in the gate, the plurality of regions provided on the gate insulating film have different work functions.Type: ApplicationFiled: December 10, 2015Publication date: August 23, 2018Inventors: Katsuhiko FUKASAKU, Takaaki TATSUMI
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Patent number: 9991253Abstract: To provide a protection element in which an increase in current due to off-state leakage can be reduced while a drive current can be ensured during an ESD operation. Provided is the protection element including: a clamp MOS transistor that has a drain coupled to a power supply line and a source coupled to a ground line; and a potential increasing circuit that increases a potential of a diffusion layer at the ground line side of the clamp MOS transistor, more than a potential of the ground line. In this protection element, the potential of the diffusion layer coupled to the ground line of the clamp MOS transistor is increased from the potential of the ground line, whereby an increase in current due to off-state leakage can be reduced while a sufficient drive current is ensured during an ESD operation.Type: GrantFiled: July 8, 2015Date of Patent: June 5, 2018Assignee: Sony Semiconductor Solutions CorporationInventor: Katsuhiko Fukasaku
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Publication number: 20170229446Abstract: To provide a protection element in which an increase in current due to off-state leakage can be reduced while a drive current can be ensured during an ESD operation. Provided is the protection element including: a clamp MOS transistor that has a drain coupled to a power supply line and a source coupled to a ground line; and a potential increasing circuit that increases a potential of a diffusion layer at the ground line side of the clamp MOS transistor, more than a potential of the ground line. In this protection element, the potential of the diffusion layer coupled to the ground line of the clamp MOS transistor is increased from the potential of the ground line, whereby an increase in current due to off-state leakage can be reduced while a sufficient drive current is ensured during an ESD operation.Type: ApplicationFiled: July 8, 2015Publication date: August 10, 2017Inventor: Katsuhiko FUKASAKU
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Patent number: 9711497Abstract: A semiconductor unit includes: a transistor configured to provide electrical conduction between a first terminal and a second terminal, based on a trigger signal; and a trigger device formed in a transistor region where the transistor is formed, and configured to generate the trigger signal, based on a voltage applied to the first terminal.Type: GrantFiled: May 7, 2014Date of Patent: July 18, 2017Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Katsuhiko Fukasaku
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Publication number: 20140339644Abstract: A semiconductor unit includes: a transistor configured to provide electrical conduction between a first terminal and a second terminal, based on a trigger signal; and a trigger device formed in a transistor region where the transistor is formed, and configured to generate the trigger signal, based on a voltage applied to the first terminal.Type: ApplicationFiled: May 7, 2014Publication date: November 20, 2014Applicant: Sony CorporationInventor: Katsuhiko Fukasaku
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Patent number: 8810982Abstract: Disclosed herein is a semiconductor integrated circuit including: a clamp MOS transistor having a drain region and a source region connected to a power source wiring and a grounding wiring, respectively, and causing a surge current to flow through a channel path and a bipolar path between the drain region and the source region; a first trigger circuit portion provided between the power source wiring and the grounding wiring, connected at an output terminal thereof to a gate terminal of the clamp MOS transistor, and controlling switching for the channel path; a second trigger circuit portion provided between the power source wiring and the grounding wiring, connected at an output terminal thereof to a well region of the clamp MOS transistor, and controlling switching for the bipolar path; and an internal circuit connected to each of the power source wiring and the grounding wiring.Type: GrantFiled: August 23, 2012Date of Patent: August 19, 2014Assignee: Sony CorporationInventor: Katsuhiko Fukasaku
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Publication number: 20130057993Abstract: Disclosed herein is a semiconductor integrated circuit including: a clamp MOS transistor having a drain region and a source region connected to a power source wiring and a grounding wiring, respectively, and causing a surge current to flow through a channel path and a bipolar path between the drain region and the source region; a first trigger circuit portion provided between the power source wiring and the grounding wiring, connected at an output terminal thereof to a gate terminal of the clamp MOS transistor, and controlling switching for the channel path; a second trigger circuit portion provided between the power source wiring and the grounding wiring, connected at an output terminal thereof to a well region of the clamp MOS transistor, and controlling switching for the bipolar path; and an internal circuit connected to each of the power source wiring and the grounding wiring.Type: ApplicationFiled: August 23, 2012Publication date: March 7, 2013Applicant: Sony CorporationInventor: Katsuhiko Fukasaku