Patents by Inventor Katsuhiko Ichinose
Katsuhiko Ichinose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200185523Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
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Publication number: 20180269323Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: May 21, 2018Publication date: September 20, 2018Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
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Patent number: 9978869Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: August 9, 2016Date of Patent: May 22, 2018Assignee: Renesas Electronics CorporationInventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20160351713Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: August 9, 2016Publication date: December 1, 2016Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
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Patent number: 9412669Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: January 22, 2015Date of Patent: August 9, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20150132904Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: January 22, 2015Publication date: May 14, 2015Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
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Patent number: 8995748Abstract: A defect image processing apparatus uses a normalized cross correlation to image-match a layout image (52) acquired from a design data with an image acquired by removing, from a defect image (53), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image (54) on the display device. In the displayed layout image & defect image (54), not only the layout image, the layer of which is the same as that of the defect image (53), but also a layout image of another layer is displayed superimposed on the defect image (53). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.Type: GrantFiled: June 1, 2010Date of Patent: March 31, 2015Assignee: Hitachi High-Technologies CorporationInventors: Tsunehiro Sakai, Shigeki Kurihara, Yutaka Tandai, Tamao Ishikawa, Yuichi Hamamura, Tomohiro Funakoshi, Seiji Isogai, Katsuhiko Ichinose
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Patent number: 8963250Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: October 15, 2008Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20140146172Abstract: Provided is a distributed image processing system for detecting an object located in a monitoring target area and an attribute of the object. An area terminal processes an image captured by a video camera, and detects whether the object of which the image is captured is present. When detecting the object located in the monitoring target area, the area terminal focuses an image capturing visual field of a digital still camera on the detected object, and inputs a release signal to the digital still camera. The area terminal transmits a still image captured by the digital still camera to a server through a network. The server processes the still image transmitted from the area terminal, and detects an attribute such as a kind and a size of the object of which the image is captured. The server performs an output according to a detection result of the object located in the monitoring target area.Type: ApplicationFiled: February 21, 2012Publication date: May 29, 2014Applicant: OMRON CORPORATIONInventors: Koichiro Kajitani, Takeshi Naito, Toru Uenoyama, Makoto Hasegawa, Katsuhiko Ichinose
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Patent number: 8595666Abstract: A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.Type: GrantFiled: May 14, 2010Date of Patent: November 26, 2013Assignee: Hitachi High-Technologies CorporationInventors: Koichi Hayakawa, Takehiro Hirai, Yutaka Tandai, Tamao Ishikawa, Tsunehiro Sakai, Kazuhisa Hasumi, Kazunori Nemoto, Katsuhiko Ichinose, Yuji Takagi
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Publication number: 20120141011Abstract: A defect image processing apparatus uses a normalized cross correlation to image-match a layout image (52) acquired from a design data with an image acquired by removing, from a defect image (53), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image (54) on the display device. In the displayed layout image & defect image (54), not only the layout image, the layer of which is the same as that of the defect image (53), but also a layout image of another layer is displayed superimposed on the defect image (53). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.Type: ApplicationFiled: June 1, 2010Publication date: June 7, 2012Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Tsunehiro Sakai, Shigeki Kurihara, Yutaka Tandai, Tamao Ishikawa, Yuichi Hamamura, Tomohiro Funakoshi, Seiji Isogai, Katsuhiko Ichinose
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Publication number: 20120131529Abstract: A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.Type: ApplicationFiled: May 14, 2010Publication date: May 24, 2012Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Koichi Hayakawa, Takehiro Hirai, Yutaka Tandai, Tamao Ishikawa, Tsunehiro Sakai, Kazuhisa Hasumi, Kazunori Nemoto, Katsuhiko Ichinose, Yuji Takagi
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Patent number: 7705402Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: August 12, 2008Date of Patent: April 27, 2010Assignee: Renesas Technology Corp.Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20090039427Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: October 15, 2008Publication date: February 12, 2009Inventors: Akihiro SHIMIZU, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20080303091Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: August 12, 2008Publication date: December 11, 2008Inventors: Akihiro SHIMIZU, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Patent number: 7414293Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.Type: GrantFiled: October 3, 2006Date of Patent: August 19, 2008Assignee: Renesas Technology Corp.Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Patent number: 7411253Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: GrantFiled: December 20, 2006Date of Patent: August 12, 2008Assignee: Renesas Technology Corp.Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20080157219Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.Type: ApplicationFiled: March 12, 2008Publication date: July 3, 2008Inventors: Tsuyoshi FUJIWARA, Masahiro Ushiyama, Katsuhiko Ichinose, Naohumi Ohashi, Tetsuo Saito
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Publication number: 20070102768Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.Type: ApplicationFiled: December 20, 2006Publication date: May 10, 2007Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
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Publication number: 20070023843Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.Type: ApplicationFiled: October 3, 2006Publication date: February 1, 2007Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Monaka, Katsuhiko Ichinose