Patents by Inventor Katsuhiko Inada
Katsuhiko Inada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240110186Abstract: A method produces a hairpin single-stranded RNA molecule capable of inhibiting expression of a target gene, including the step of reacting a first single-stranded oligo-RNA molecule represented by formula (I) with a second single-stranded oligo-RNA molecule represented by formula (II) in a mixed solvent including a buffer solution and a hydrophilic organic solvent in the presence of a dehydration condensation agent: 5?-Xc-Lx1 . . . (I) and Lx2-X—Y-Ly-Yc-3? . . . (II), wherein the dehydration condensation agent is selected from the group consisting of a triazine-based dehydration condensation agent, a uronium-based dehydration condensation agent including an N-hydroxy nitrogen-containing aromatic ring structure, a carbodiimide-based dehydration condensation agent, a 2-halopyridinium-based dehydration condensation agent, and a formamidinium-based dehydration condensation agent.Type: ApplicationFiled: September 1, 2023Publication date: April 4, 2024Inventors: Kyohei Koshimoto, Katsuhiko Iseki, Hideaki Inada, Tatsuya Fujita, Keiichi Okimura, Munetaka Kunishima, Tadaaki Ohgi, Eriko Aoki
-
Patent number: 11920131Abstract: A method produces a hairpin single-stranded RNA molecule capable of inhibiting expression of a target gene, the method including: (i) an annealing step of annealing a first single-stranded oligoRNA molecule and a second single-stranded oligoRNA molecule; and (ii) a ligation step of ligating 3? end of the first single-stranded oligoRNA molecule and 5? end of the second single-stranded oligoRNA molecule by an Rnl2 family ligase, wherein a sequence produced by ligating the first single-stranded oligoRNA molecule and the second single-stranded oligoRNA molecule includes a gene expression-inhibiting sequence for the target gene.Type: GrantFiled: March 29, 2019Date of Patent: March 5, 2024Assignee: Toray Industries, Inc.Inventors: Hideaki Inada, Katsuhiko Iseki, Keiichi Okimura, Masato Sanosaka, Ayumi Takashina
-
Patent number: 7564511Abstract: A circuit array substrate includes an optically transparent substrate, pixels having switching elements formed on the transparent substrate, gate electrode lines connected to the switching elements, the gate electrode lines being provided on a first insulation film with separating portions in the pixels, signal lines connected to the switching elements, the signal lines being provided on a second insulation film which is different from the first insulation film, and electrically conductive portions provided on the second film to electrically connect the electrode lines with the separating portions to each other. The separating portions reduce electrostatic capacitances defined between the gate electrode lines and the switching elements when the conductive portions are not connected between the separating portions.Type: GrantFiled: October 21, 2004Date of Patent: July 21, 2009Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Hiroshi Tabatake, Tetsuya Kawamura, Shinichi Kawamura, Katsuhiko Inada, Atsushi Takeda, Nobuo Imai, Akihiro Takami
-
Patent number: 7557373Abstract: A thin-film transistor substrate includes a pixel region where gate electrode lines are arranged on an insulating substrate sandwiching semiconductor layer patterns and a gate insulator with the insulating substrate, wherein shapes of the semiconductor patterns and the gate electrode lines are set so that a value of K obtained by the following equation is smaller than a first set value when the thin-film transistor substrate is mounted on a metal table: K=(L/Ce)×{Ca/(Ca+Cb)}×S where Ca represents a capacitor between each of the semiconductor layer patterns and the metal table, Cb represents a capacitor between each of the semiconductor layer patterns and the gate electrode lines, Ce represents a capacitor between each of the gate electrode lines and the metal table, L represents a length of each of the gate electrode line, and S represents a substrate surface area that one of the gate electrode lines are in charge of per unit length.Type: GrantFiled: March 21, 2005Date of Patent: July 7, 2009Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Tetsuya Kawamura, Katsuhiko Inada
-
Patent number: 7545475Abstract: To suppress occurrence of low temperature bubbles while securing pressure resistance to external forces applied to substrates of a liquid crystal display device, a plurality of spacers disposed between the substrates are divided into a plurality of spacer groups 2, one unit of which is configured with spacers 2a, 2b allocated in close proximity to each other; and the spacer groups 2 are disposed with a density that the low temperature bubbles do not occur. Hence, the strength of the substrates increases, and in a region 10 where no spacers exist, a large deformation of the substrates by shrinkage is allowed, and a liquid crystal layer 8 is sufficiently enough shrunk even under a low temperature environment to prevent the low temperature bubbles from occurring.Type: GrantFiled: May 17, 2006Date of Patent: June 9, 2009Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Tetsuya Kawamura, Katsuhiko Inada, Akimasa Toyama
-
Publication number: 20080061294Abstract: A thin-film transistor substrate includes a pixel region where gate electrode lines are arranged on an insulating substrate sandwiching semiconductor layer patterns and a gate insulator with the insulating substrate, wherein shapes of the semiconductor patterns and the gate electrode lines are set so that a value of K obtained by the following equation is smaller than a first set value when the thin-film transistor substrate is mounted on a metal table: K=(L/Ce)×{Ca/(Ca+Cb)}×S where Ca represents a capacitor between each of the semiconductor layer patterns and the metal table, Cb represents a capacitor between each of the semiconductor layer patterns and the gate electrode lines, Ce represents a capacitor between each of the gate electrode lines and the metal table, L represents a length of each of the gate electrode line, and S represents a substrate surface area that one of the gate electrode lines are in charge of per unit length.Type: ApplicationFiled: November 8, 2007Publication date: March 13, 2008Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Tetsuya Kawamura, Katsuhiko Inada
-
Patent number: 7291659Abstract: There are provided a water dispersion for ink-jet printing comprising colorant-containing water-insoluble graft polymer particles in which the water-insoluble graft polymer contains a main chain which is a polymer chain containing a constitutional unit derived from a salt-forming group-containing monomer (a) and a constitutional unit derived from an aromatic ring-containing (meth)acrylate monomer (b), and a side chain which is a polymer chain containing a constitutional unit derived from a hydrophobic monomer (c); a water-based ink for ink-jet printing using the water dispersion; and an ink-jet printing method using the water-based ink. In accordance with the present invention, printed images or characters formed on a coated paper are excellent in gloss, image clarity and image clarity property including both of the image clarity and the gloss, and printed images or characters formed on an ordinary paper exhibit a high print density.Type: GrantFiled: July 28, 2005Date of Patent: November 6, 2007Assignee: KAO CorporationInventors: Isao Tsuru, Ryuma Mizushima, Katsuhiko Inada, Takehiro Tsutsumi
-
Publication number: 20060285057Abstract: To suppress occurrence of low temperature bubbles while securing pressure resistance to external forces applied to substrates of a liquid crystal display device, a plurality of spacers disposed between the substrates are divided into a plurality of spacer groups 2, one unit of which is configured with spacers 2a, 2b allocated in close proximity to each other; and the spacer groups 2 are disposed with a density that the low temperature bubbles do not occur. Hence, the strength of the substrates increases, and in a region 10 where no spacers exist, a large deformation of the substrates by shrinkage is allowed, and a liquid crystal layer 8 is sufficiently enough shrunk even under a low temperature environment to prevent the low temperature bubbles from occurring.Type: ApplicationFiled: May 17, 2006Publication date: December 21, 2006Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Tetsuya Kawamura, Katsuhiko Inada, Akimasa Toyama
-
Patent number: 7088328Abstract: A signal line driving circuit makes the polarities of video signals different from each other, the video signal being supplied to pixel electrodes adjacent to an arbitrary pixel electrode on both sides thereof in a horizontal scanning direction. The signal line driving circuit also makes the polarities of video signals different from each other, the video signal being supplied to pixel electrodes adjacent to the arbitrary pixel electrode on both sides thereof in a vertical scanning direction. A signal line driving IC outputs the video signal to each signal line group obtained by dividing a plurality of signal lines to a plurality of signal line groups composed of a predetermined number of the signal lines. A signal line switching circuit switches all of the signal lines in each signal line group sequentially during one horizontal scanning period.Type: GrantFiled: November 13, 2002Date of Patent: August 8, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Inada, Yasuyuki Hanazawa, Tetsuo Morita, Kohei Nagayama, Hideyuki Takahashi
-
Publication number: 20060030640Abstract: There are provided a water dispersion for ink-jet printing comprising colorant-containing water-insoluble graft polymer particles in which the water-insoluble graft polymer contains a main chain which is a polymer chain containing a constitutional unit derived from a salt-forming group-containing monomer (a) and a constitutional unit derived from an aromatic ring-containing (meth)acrylate monomer (b), and a side chain which is a polymer chain containing a constitutional unit derived from a hydrophobic monomer (c); a water-based ink for ink-jet printing using the water dispersion; and an ink-jet printing method using the water-based ink. In accordance with the present invention, printed images or characters formed on a coated paper are excellent in gloss, image clarity and image clarity property including both of the image clarity and the gloss, and printed images or characters formed on an ordinary paper exhibit a high print density.Type: ApplicationFiled: July 28, 2005Publication date: February 9, 2006Applicant: KAO CORPORATIONInventors: Isao Tsuru, Ryuma Mizushima, Katsuhiko Inada, Takehiro Tsutsumi
-
Publication number: 20050218402Abstract: A thin-film transistor substrate includes a pixel region where gate electrode lines are arranged on an insulating substrate sandwiching semiconductor layer patterns and a gate insulator with the insulating substrate, wherein shapes of the semiconductor patterns and the gate electrode lines are set so that a value of K obtained by the following equation is smaller than a first set value when the thin-film transistor substrate is mounted on a metal table: K=(L/Ce)×{Ca/(Ca+Cb)}×S where Ca represents a capacitor between each of the semiconductor layer patterns and the metal table, Cb represents a capacitor between each of the semiconductor layer patterns and the gate electrode lines, Ce represents a capacitor between each of the gate electrode lines and the metal table, L represents a length of each of the gate electrode line, and S represents a substrate surface area that one of the gate electrode lines are in charge of per unit length.Type: ApplicationFiled: March 21, 2005Publication date: October 6, 2005Applicant: TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO., LTD.Inventors: Tetsuya Kawamura, Katsuhiko Inada
-
Publication number: 20050140570Abstract: Gate electrode lines 11 formed on glass substrate 3 are separated by separating portions 32 for respective pixels 5 to shorten lengths of gate electrode lines 11. Both end portions of gate electrode lines 11 separated by separating portions 32 are electrically connected by conductive films 42 made from the same materials as signal electrode lines 13. When glass substrate 3 is lifted up while glass substrate 3 is charged with static electricity, the increases in voltages at gate insulation film 31 provided between gate electrode lines 11 and polycrystalline semiconductor film 22 are effectively suppressed so that electrostatic destruction of gate electrode lines 11 can be prevented.Type: ApplicationFiled: October 21, 2004Publication date: June 30, 2005Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Hiroshi Tabatake, Tetsuya Kawamura, Shinichi Kawamura, Katsuhiko Inada, Atsushi Takeda, Nobuo Imai, Akihiro Takami
-
Patent number: 6839119Abstract: A display device includes a substrate (100), pixel electrodes (PIX) formed on the substrate (100), scanning lines (G) to transmit scanning signals, signal lines (S) divided into four groups (LL, LR, RL and RR) to transmit data signals, signal line driving circuits (112) to drive the groups (LL, LR, RL and RR) of the signal lines (S), respectively, analog switch control signal lines (107 and 108) connected between the signal line driving circuits (112) and the groups (LL, LR, RL and RR) of the signal lines (S), and transistors (ASW) connected between the analog switch control signal lines (107 and 108) and the groups (LL, LR, RL and RR) of the signal lines (S) to provide the data signals to the pixel electrodes (PIX) in response to the scanning signals.Type: GrantFiled: May 19, 2003Date of Patent: January 4, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Sasaki, Katsuhiko Inada, Tetsuo Morita, Koichi Shiba
-
Publication number: 20030234902Abstract: A display device includes a substrate (100), pixel electrodes (PIX) formed on the substrate (100), scanning lines (G) to transmit scanning signals, signal lines (S) divided into four groups (LL, LR, RL and RR) to transmit data signals, signal line driving circuits (112) to drive the groups (LL, LR, RL and RR) of the signal lines (S), respectively, analog switch control signal lines (107 and 108) connected between the signal line driving circuits (112) and the groups (LL, LR, RL and RR) of the signal lines (S), and transistors (ASW) connected between the analog switch control signal lines (107 and 108) and the groups (LL, LR, RL and RR) of the signal lines (S) to provide the data signals to the pixel electrodes (PIX) in response to the scanning signals.Type: ApplicationFiled: May 19, 2003Publication date: December 25, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasushi Sasaki, Katsuhiko Inada, Tetsuo Morita, Koichi Shiba
-
Publication number: 20030090450Abstract: A signal line driving circuit makes the polarities of video signals different from each other, the video signal being supplied to pixel electrodes adjacent to an arbitrary pixel electrode on both sides thereof in a horizontal scanning direction. The signal line driving circuit also makes the polarities of video signals different from each other, the video signal being supplied to pixel electrodes adjacent to the arbitrary pixel electrode on both sides thereof in a vertical scanning direction. A signal line driving IC outputs the video signal to each signal line group obtained by dividing a plurality of signal lines to a plurality of signal line groups composed of a predetermined number of the signal lines. A signal line switching circuit switches all of the signal lines in each signal line group sequentially during one horizontal scanning period.Type: ApplicationFiled: November 13, 2002Publication date: May 15, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiko Inada, Yasuyuki Hanazawa, Tetsuo Morita, Kohei Nagayama, Hideyuki Takahashi
-
Patent number: 6271600Abstract: A redundant wiring apparatus used for a liquid crystal display apparatus and a method of a making the same are disclosed. The liquid crystal display device includes a switching circuit array substrate and a counter substrate provided opposite to the array substrate. Signal and scanning lines are disposed on the array substrate in a matrix form. The signal and scanning lines are connected pixel electrodes through the switching circuits formed on the array substrate. A display region and a surrounding region are provided on the array substrate. The signal and scanning lines have lead wires extending from the display region to the surrounding region. The lead wires are redundant in wiring structure in which a first wire, an insulation layer and a second wire are laminated. The first and second wires are electrically connected through connectors received in through-holes at both ends of the first wire. Repair portions of the first and second wires are provided in the vicinity of through-holes.Type: GrantFiled: August 31, 1998Date of Patent: August 7, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Inada
-
Patent number: 6030265Abstract: A method of manufacturing an array substrate for a display device having a surface area including a display area having a plurality of pixel electrode arranged on a main surface of an insulating substrate, a peripheral area positioned at the outside of the display area to supply a drive voltage to the display area, and a mark area positioned at the outside of the peripheral area, including the steps of forming a first layer on a main surface of the insulating substrate, forming a resist on the first layer, and patterning the first layer by exposing the resist using a plurality of mask patterns which correspond to each area obtained by dividing of the surface area, wherein adjacent divided areas of the first substrate area and the second substrate area are patterned with a common mask having two mask patterns each used in each of the first substrate area and the second substrate area of each area obtained by dividing of the surface area.Type: GrantFiled: July 17, 1997Date of Patent: February 29, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Inada
-
Patent number: 5835171Abstract: The present invention relates to the structure of an active matrix type liquid crystal display device in which a channel length of a thin film transistor without increasing resistance of a scanning line region to improve a switching characteristic. A slit is formed at the channel of the thin film transistor formed on the scanning line region. The slit is used as a mask and a pattern of a channel protection film for determining the channel of the thin film transistor is formed by exposure form a back surface of a substrate. According to this method, a desirable channel length can be obtained, and the scanning line region, facing to the channel through the slit, functions as an auxiliary region, so that the resistance of the scanning line region can be reduced.Type: GrantFiled: October 11, 1996Date of Patent: November 10, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Yasuyuki Hanazawa, Tomoko Kitazawa, Yoshihiro Asai, Katsuhiko Inada, Tetsuya Iizuka
-
Patent number: 5784135Abstract: An object of the technology of our invention is to solve a luminance defect viewed as a "seam" or the like and to provide a liquid crystal display device having a screen for equally displaying an image. For example, when an exposing process is performed for one conductor layer or a dielectric layer, a total of four photomasks are used corresponding to four shot areas. A light insulation layer of a photomask used for the exposing process for patterning for example a signal line is formed so that it becomes a projection pattern of the signal line. The photomasks corresponding to adjacent shot areas are formed so that patterns of the light insulation layers of the boundary portion are engaged with each other on the plane.Type: GrantFiled: October 3, 1996Date of Patent: July 21, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Inada, Osamu Shimada, Masahiro Seiki, Ryuji Tada, Atsushi Sugahara
-
Patent number: 5656526Abstract: An object of the technology of our invention is to solve a luminance defect viewed as a "seam" or the like and to provide a liquid crystal display device having a screen for equally displaying an image. For example, when an exposing process is performed for one conductor layer or a dielectric layer, a total of four photomasks are used corresponding to four shot areas. A light insulation layer of a photomask used for the exposing process for patterning for example a signal line is formed so that it becomes a projection pattern of the signal line. The photomasks corresponding to adjacent shot areas are formed so that patterns of the light insulation layers of the boundary portion are engaged with each other on the plane.Type: GrantFiled: November 7, 1995Date of Patent: August 12, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Inada, Osamu Shimada, Masahiro Seiki, Ryuji Tada, Atsushi Sugahara