Abstract: Formation of a photomask in the conventional art requires significant cost and time. The invention provides a patterning method of forming a desired latent image pattern by irradiating a resist film formed on a substrate with focused light beam. The method comprising adjusting intensity of the focused light beam or size thereof on the resist film depending on a design of the pattern to irradiate the resist film, thereby achieving a desired pattern with reasonable cost and time.

Abstract: A plasma processing apparatus includes a vacuum processing chamber having a pair of opposing electrodes for plasma generation, one electrode serving as a sample table for a sample including an insulator film. An electrostatic adsorption film is arranged at the sample table electrode to supply a thermal conductive gas between the film and the sample rear surface. A pressure reducing element is also provided. In addition, arrangements are provided to set a gas pressure within said vacuum processing chamber to 0.5 to 4.0 Pa and to apply a high frequency power of 30 MHz to 200 MHz between the electrodes. An electrode cover is disposed at the other electrode, and a clearance between the electrodes is 30 mm to 100 mm.

Abstract: A method of plasma-processing is provided which includes placing a sample on one of electrodes provided in a vacuum processing chamber and holding the sample onto the electrodes by an electrostatic attracting force. A processing gas is introduced into an environment in which said sample is placed, and the environment is evacuated to a pressure condition for processing said sample. The processing gas is then formed into a plasma under the pressure condition, the sample is processed by the plasma, and a pulse bias voltage having a pulse cycle of 0.1 ?m to 10 ?m is applied to the sample.

Abstract: A plasma processing apparatus includes a vacuum processing chamber having a pair of opposing electrodes for plasma generation, one electrode serving as a sample table for a sample including an insulator film. An electrostatic adsorption film is arranged at the sample table electrode to supply a thermal conductive gas between the film and the sample rear surface. A pressure reducing element is also provided. In addition, arrangements are provided to set a gas pressure within said vacuum processing chamber to 0.5 to 4.0 Pa and to apply a high frequency power of 30 MHz to 200 MHz between the electrodes. An electrode cover s disposed at the other electrode, and a clearance between the electrodes is 30 mm to 100 mm.

Abstract: A plasma processing apparatus includes a vacuum processing chamber having a pair of opposing electrodes for plasma generation, one electrode serving as a sample table for a sample including an insulator film. An electrostatic adsorption film is arranged at the sample table electrode to supply a thermal conductive gas between the film and the sample rear surface. A pressure reducing element is also provided. In addition, arrangements are provided to set a gas pressure within said vacuum processing chamber to 0.5 to 4.0 Pa and to apply a high frequency power of 30 MHz to 200 MHz between the electrodes. An electrode cover is disposed at the other electrode, and a clearance between the electrodes is 30 mm to 100 mm.

Abstract: A plasma processing apparatus and a plasma processing method are provided. The plasma processing apparatus and a plasma processing method are capable of easily performing precise working of a fine pattern to a large sized sample having a diameter of 300 mm or larger, and also capable of improving a selectivity during micro processing.

Abstract: A plasma processing apparatus and a method therefor which can achieve a preferred process rate, a fine pattern process capability, a selectivity and uniformity of processing at the same time compatibly for a large size wafer, which effects are achieved by controlling the plasma state and the dissociation state of etching gas through control of the electron resonance through application of a magnetic field thereto. A high frequency power at 20-300 MHz is applied across a pair of electrodes in a vacuum process chamber, and a magnetic field is formed parallel to the plane of the electrodes in the space between the electrodes. By controlling the intensity of the magnetic field in a range of 100 gauss or smaller, formation of electron cyclotron resonance and electron sheath resonance occurring from interaction between the electrical field and the magnetic field in the electrode sheath portion is controlled. Thereby, the plasma state, i.e.

Abstract: A plasma processing apparatus comprising a vacuum processing chamber, a plasma generating means including a pair of electrodes, a sample table for mounting a sample to be processed inside the vacuum processing chamber and also serving as one of the electrodes, and a evacuating means for evacuating the vacuum processing chamber, which further comprises a high frequency electric power source for applying an electric power of a VHF band from 50 MHz to 200 MHz between the pair of electrodes; and a magnetic field forming means for forming a static magnetic field or a low frequency magnetic field larger than 10 gausses and smaller than 110 gausses in a direction intersecting an electric field generated between the pair of electrodes and the vicinity by the high frequency electric power source; therein the magnetic field forming means being set so that a portion where a component of the magnetic field in a direction along the surface of the sample table becomes maximum is brought to a position in the opposite side o

Abstract: A plasma processing apparatus and method are provided which are capable of easily performing precise working of a fine pattern on a large sized sample having a diameter of 300 mm or larger, and also capable of improving selectivity during micro processing. The apparatus includes a vacuum processing chamber, a plasma generating arrangement including a pair of electrodes, a sample table for mounting a sample to be processed inside the vacuum processing chamber and also serving as one of the electrodes, and an evacuating means for evacuating the vacuum processing chamber. The apparatus further includes a high frequency electric power source for applying an electric power of VHF band from 50 MHz to 200 MHz between the pair of electrodes.

Abstract: A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.

Abstract: A method may be used to dry etch a sample including a plurality of regions different from each other in the photo-absorption of a light having a specified wavelength using an etching gas plasma. The method is capable of selectively etching the desired material from a plurality of materials having different types of band gap energies or from a plurality of materials having different band gap energies. The method includes a step of irradiating a light having the specified wavelength on the sample for reducing an etching rate of a region having a large photo-absorption coefficient to the light, thereby selectively etching a region having a small photo-absorption coefficient to the light.

Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.

Abstract: A hetero junction bipolar transistor provides a contact area an area between an emitter (or collector) electrode and a wiring formed on the electrode that is larger than that of the emitter (or collector). A variation in voltage applied to an emitter (or collector)-base junctions is prevented and a stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask. A patterning of the emitter (or collector) is then carried out and thus an emitter (or collector) having a size approximate to that of the mask is formed.

Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by introduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.

Abstract: Disclosed is a semiconductor device including a heterojunction bipolar transistor in which the front surface of a base layer and the surface of an emitter-base junction are covered with a high-resistivity layer of compound semiconductor containing at least one constituent element common to an emitter layer and the base layer.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.

Abstract: Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.

Abstract: 2A heterojunction bipolar transistor is disclosed in which a region of a base layer which extends in the vicinity of the interface between the base layer and an emitter layer is doped with an impurity at a higher concentration than that in the inside of the base layer to thereby form a built-in field by which carriers injected from the emitter are caused to drift to the inside of the base layer. In the transistor having this structure, the current gain does not depend on the emitter area, and it is possible to obtain a large current gain with a small emitter area.